Memory Controller for a Memory Device

1. A memory controller for a memory device, the memory controller comprising: a command generator configured to generate a command signal based on a system clock signal, and to generate phase difference information for the command signal; and a memory interface configured to receive the command signal and the phase difference information from the command generator, to adjust a timing of the command signal based on the phase difference information, and transmit the command signal of which the timing is adjusted as a timing adjusted command signal to the memory device, wherein the phase difference information represents a phase difference between the command signal generated based on the system clock signal and a standard command signal having a standard timing defined in a controller-memory interface standard.

2. The memory controller of claim 1, wherein, to adjust the timing of the command signal generated based on the system clock signal, the memory interface delays the command signal by a delay time corresponding to the phase difference represented by the phase difference information.

3. The memory controller of claim 1, wherein the command generator includes: a phase generation circuit configured to generate the phase difference information.

4. The memory controller of claim 1, wherein the memory interface includes: a phase control circuit configured to generate a delay control value based on the phase difference information; and a delay line configured to delay the command signal output from the command generator by a delay time corresponding to the phase difference represented by the phase difference information based on the delay control value.

5. The memory controller of claim 4, wherein the phase control circuit receives a clock lock value corresponding to a cycle time of the system clock signal, and calculates the delay control value based on the phase difference represented by the phase difference information, a resolution value of the phase difference and the clock lock value.

6. The memory controller of claim 5, wherein the phase control circuit calculates the delay control value by using an equation, “DCV=(PD/PRV)*CLV”, where DCV represents the delay control value, PD represents the phase difference represented by the phase difference information, PRV represents the resolution value of the phase difference, and CLV represents the clock lock value.

7. The memory controller of claim 5, wherein the resolution value of the phase difference is settable.

8. The memory controller of claim 4, wherein the delay line includes: a coarse delay line configured to delay the command signal output from the command generator by a first interval in response to at least one most significant bit of the delay control value; and a fine delay line configured to delay the command signal output by the coarse delay line by a second interval narrower than the first interval in response to at least one least significant bit of the delay control value.

9. The memory controller of claim 4, wherein the memory interface further includes: a delay locked loop circuit configured to receive the system clock signal, and to generate a clock lock value corresponding to a cycle time of the system clock signal.

10. The memory controller of claim 9, wherein the delay locked loop circuit includes: a digital control delay line configured to generate an output clock signal by delaying the system clock signal; a phase detector configured to detect a phase difference between the system clock signal and the output clock signal; and a delay control circuit configured to control a delay time of the digital control delay line based on the phase difference detected by the phase detector, and to generate the clock lock value corresponding to the cycle time of the system clock signal.

11. The memory controller of claim 4, wherein the memory interface further includes: a flip-flop configured to capture the command signal output from the command generator in response to the system clock signal, and to output the captured command signal to the delay line.

12. The memory controller of claim 1, further comprising: a clock generator configured to generate the system clock signal, and to provide the system clock signal to the command generator and the memory interface.

13. A memory controller for a memory device, the memory controller comprising: a command generator configured to generate a command signal based on a system clock signal, and to generate phase difference information for the command signal; and a memory interface configured to receive the command signal and the phase difference information from the command generator, to adjust a timing of the command signal based on the phase difference information, and transmit the command signal of which the timing is adjusted as a timing adjusted command signal to the memory device, wherein the memory interface includes: a phase control circuit configured to generate a select signal based on the phase difference information; a plurality of flip-flops configured to capture the command signal output from the command generator in response to an input/output clock signal; and a multiplexer configured to select, as the timing adjusted command signal, one of output signals of the plurality of flip-flops in response to the select signal.

14. The memory controller of claim 13, wherein the plurality of flip-flops includes: a plurality of rising edge-triggered flip-flops connected in series, and configured to capture the command signal output from the command generator in response to a rising edge of the input/output clock signal; and a plurality of falling edge-triggered flip-flops connected in series, and configured to capture the command signal output from the command generator in response to a falling edge of the input/output clock signal.

15. A memory controller for a memory device, the memory controller comprising: a clock generator configured to generate a system clock signal; a command generator configured to generate a command signal in response to the system clock signal; and a memory interface configured to transmit a timing adjusted command signal to the memory device, wherein the command generator includes: a phase generation circuit configured to generate phase difference information representing a phase difference between the command signal and a standard command signal, and wherein the memory interface includes: a delay locked loop circuit configured to generate a clock lock value corresponding to a cycle time of the system clock signal; a phase control circuit configured to generate a delay control value based on the phase difference represented by the phase difference information, a resolution value of the phase difference and the clock lock value; and a phase application circuit configured to adjust a timing of the command signal by the phase difference represented by the phase difference information based on the delay control value and to output the command signal with the adjusted timing as the timing adjusted command signal.

16. The memory controller of claim 15, wherein the phase application circuit includes: a delay line configured to delay the command signal by a delay time corresponding to the phase difference represented by the phase difference information based on the delay control value.