Scoreboard for Register Data Cache

1. An apparatus, comprising: datapath circuitry configured to execute instructions that operate on input operands from architectural registers; data cache circuitry configured to cache architectural register data for the datapath circuitry; one or more backing caches or memories configured to store architectural register data evicted from the data cache circuitry; scoreboard circuitry configured to track, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry; and a pointer to the entry of the data cache circuitry.

2. The apparatus of claim 1, wherein the apparatus is configured to determine hits and misses in the data cache circuitry by accessing the scoreboard circuitry using thread identifier information and register identifier information.

3. The apparatus of claim 1, wherein the scoreboard circuitry is further configured to track, for a given architectural register: an indication whether a mapped architectural register has valid data in the data cache circuitry; an indication whether an architectural register is locked by the datapath circuitry such that it is not currently allowed to be evicted from the data cache circuitry; an indication whether a long-latency operation is pending for the architectural register; an indication whether a fill data return is pending for the architectural register; and an indication whether an eviction is pending for the architectural register.

4. The apparatus of claim 1, wherein: in response to a processor event, the scoreboard circuitry is configured to save map information for multiple corresponding architectural registers to at least one of the one or more backing caches or memories; and the scoreboard circuitry is configured to restore the map information to the scoreboard circuitry in response to a restore event.

5. The apparatus of claim 1, further comprising cache control circuitry configured to: select an entry in the data cache circuitry for eviction based on a priority of a thread corresponding to the entry.

6. The apparatus of claim 1, wherein the data cache circuitry includes: first-level storage circuitry configured to provide operand data directly to the datapath circuitry; and second-level storage circuitry configured to provide fill data to the first-level storage circuitry; wherein the scoreboard circuitry is configured to maintain map state information that indicates whether mapped register data exists in the first-level storage circuitry or the second-level storage circuitry.

7. The apparatus of claim 6, wherein the data cache circuitry is configured to allocate an entry in the second-level storage circuitry for a register based on a compiler hint that indicates a long-latency operation is pending to obtain data for the register.

8. The apparatus of claim 1, further comprising: channel pipelines; execution pipelines configured to receive instructions from the channel pipelines; thread scheduling circuitry configured to arbitrate among threads to select threads to activate to a channel pipeline; and instruction scheduling circuitry configured to arbitrate among instructions in channel pipelines to schedule to the execution pipelines; wherein the scoreboard circuitry includes: first scoreboard circuitry implemented using a first circuit technology and configured to store scoreboard information for one or more activated threads; second scoreboard circuitry implemented using a second circuit technology and configured to store scoreboard information for one or more inactive threads; and control circuitry configured to copy data from the second scoreboard circuitry to the first scoreboard circuitry in response to a thread activation.

9. The apparatus of claim 8, wherein the first circuit technology is a flop-based technology and the second circuit technology is a random-access memory.

10. The apparatus of claim 8, further comprising: eviction candidate circuitry configured to store information from the scoreboard circuitry for one or more deactivated threads; and control circuitry configured to evict data from the data cache circuitry based on information stored in the eviction candidate circuitry.

11. The apparatus of claim 10, wherein the control circuitry is configured to evict the data based on occupancy of the data cache circuitry reaching a threshold level.

12. The apparatus of claim 8, further comprising cache control circuitry configured to: select an entry in the data cache circuitry for eviction according to a policy that prioritizes data from inactive threads for eviction over data from activated threads.

13. The apparatus of claim 8, wherein: the first scoreboard circuitry includes multiple banks; and the second scoreboard circuitry includes multiple storage instances that each include scoreboard information from multiple banks of the first scoreboard circuitry.

14. The apparatus of claim 1, wherein the apparatus is a computing device that further includes: a central processing unit; a display; and network interface circuitry.

15. The apparatus of claim 1, wherein the datapath circuitry includes a plurality of single-instruction multiple-data (SIMD) pipelines configured to execute instructions; and wherein the apparatus includes fixed-function circuitry configured to control the SIMD pipelines to perform operations for at least one of the following types of programs: graphics shader programs; and machine learning programs.

16. A method, comprising: caching, by a computing system in a data cache, architectural register data; storing, by the computing system, architectural register data evicted from the data cache; tracking, by the computing system using a scoreboard, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache; and a pointer to the entry of the data cache.

17. The method of claim 16, wherein the tracking further tracks: an indication whether the architectural register is locked by a datapath such that it is not currently allowed to be evicted from the data cache; and an indication whether a long-latency operation is pending for the architectural register.

18. The method of claim 16, further comprising: saving, by the computing system in response to a processor event, map information for multiple corresponding architectural registers; and restoring, by the computing system, the saved map information to the scoreboard in response to a restore event.

19. The method of claim 16, further comprising: selecting an entry in the data cache for eviction based on a priority of a thread corresponding to the entry.

20. A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes: datapath circuitry configured to execute instructions that operate on input operands from architectural registers; data cache circuitry configured to cache architectural register data for the datapath circuitry; one or more backing caches or memories configured to store architectural register data evicted from the data cache circuitry; scoreboard circuitry configured to track, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry; and a pointer to the entry of the data cache circuitry.