ASTC Interpolation

1. A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 for generating an interpolated result P, the values E0 and E1 being formed from low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the binary logic circuit being configured to: perform an interpolation between the colour endpoint values C0 and C1 to generate a first intermediate interpolated result C2; and determine the interpolated result P such that the interpolated result P satisfies the equation P=└((C2<<8)+C2+32)/64┘, or satisfies the equation P=└((C2<<8)+128·64+32)/64┘.

2. The binary logic circuit as claimed in claim 1, wherein the interpolation calculation between the two endpoint values E0 and E1 is specified such that p=└(E0·(64−i)+E1·i+32)/64┘, where p is equal to the interpolated result P, and i is a weighting index.

3. The binary logic circuit as claimed in claim 1, wherein the binary logic circuit is further configured to perform the interpolation between the colour endpoint values C0 and C1 using a weighting index i to generate the first intermediate interpolated result C2 such that C2=C0·(64−i)+C1·i for non-exception values of i.

4. The binary logic circuit as claimed in claim 3, wherein the binary logic circuit is further configured to generate the first intermediate interpolated result C2 for exception values of i.

5. The binary logic circuit as claimed in claim 4, wherein the binary logic circuit is further configured to generate the first intermediate interpolated result C2 such that C2=C1·i for exception values of i.

6. The binary logic circuit as claimed in claim 4, wherein the binary logic circuit is further configured to: generate a second intermediate interpolated result from the set of values C0, C1 and C2; left-shift the second intermediate interpolated result by a number of bits equal to the number of bits of each of the colour endpoint values C0 and C1 and to add to the shifted result a constant to generate a third intermediate interpolated result; and add the second intermediate interpolated result to the third intermediate interpolated result if the interpolated result P is not to be compatible with the sRGB colour space; wherein the binary logic circuit is further configured to generate the second intermediate interpolated result as: (i) the first intermediate interpolated result C2, such that C2=C0·(64−i)+C1·i for non-exception values of i, when the interpolated result P is not to be compatible with an sRGB colour space and the value of the weighting index is not equal to an exception value; (ii) the summation of the first intermediate interpolated result C2, such that C2=C0·(64−i)+C1·i for non-exception values of i, and a numerical constant when the interpolated result P is to be compatible with an sRGB colour space and the value of the weighting index is not equal to an exception value; (iii) the first intermediate interpolated result C2 generated for exception values of i when the interpolated result P is not to be compatible with an sRGB colour space and the value of the weighting index is equal to an exception value; and iv) the summation of the first intermediate interpolated result C2 generated for exception values of i and a numerical constant when the interpolated result P is to be compatible with an sRGB colour space and the value of the weighting index is equal to an exception value.

7. The binary logic circuit as claimed in claim 4, wherein the binary logic circuit is further configured to: generate a second intermediate interpolated result from the set of values C0, C1 and C2; left-shift the second intermediate interpolated result by a number of bits equal to the number of bits of each of the colour endpoint values C0 and C1 and to add to the shifted result a constant to generate a third intermediate interpolated result; and add the second intermediate interpolated result to the third intermediate interpolated result if the interpolated result P is not to be compatible with the sRGB colour space; wherein the binary logic circuit is further configured to: select between (i) a first input dependent on the first intermediate interpolated result C2 generated for exception values of i; and (ii) a second input dependent on the first intermediate interpolated result C2, such that C2=C0·(64−i)+C1·i for non-exception values of i, in dependence on whether the value of the weighting index is equal to an exception value.

8. The binary logic circuit as claimed in claim 7, wherein the binary logic circuit is further configured to add a non-zero numerical constant in the generation of the second intermediate interpolated result from the set of values C0, C1 and C2 only if the interpolated result P is to be compatible with an sRBG colour space.

9. The binary logic circuit as claimed in claim 8, wherein the binary logic circuit is configured to add a non-zero numerical constant to the result of the selection between the first input and the second input.

10. The binary logic circuit as claimed in claim 8, wherein the binary logic circuit is configured to generate the second intermediate interpolated result based on the first intermediate interpolated result C2 generated for exception values of i, and the first intermediate interpolated result C2, such that C2=C0·(64−i)+C1·i for non-exception values of i.

11. The binary logic circuit as claimed in claim 7, wherein the first input is the first intermediate interpolated result C2 generated for exception values of i and the second input is the first intermediate interpolated result C2, such that C2=C0·(64−i)+C1·i for non-exception values of i.

12. The binary logic circuit as claimed in claim 3, wherein the weighting index comprises 7 bits, and the binary logic circuit is configured to perform the interpolation between the colour endpoint values C0 and C1 using the 6 least significant bits of the weighting index.

13. The binary logic circuit as claimed in claim 1, wherein the binary logic circuit is further configured to: generate a second intermediate interpolated result from the set of values C0, C1 and C2 in dependence on whether the interpolated result P is to be compatible with an sRGB colour space; left-shift the second intermediate interpolated result by a number of bits equal to the number of bits of each of the colour endpoint values C0 and C1 and to add to the shifted result a constant to generate a third intermediate interpolated result; and add the second intermediate interpolated result to the third intermediate interpolated result if the interpolated result P is not to be compatible with the sRGB colour space.

14. The binary logic circuit as claimed in claim 13, wherein the binary logic circuit is further configured to right-shift the result of adding the second intermediate interpolated result to the third intermediate interpolated result by a specified number of bits to generate the interpolated result P.

15. The binary logic circuit as claimed in claim 14, wherein the specified number of bits is equal to 6.

16. The binary logic circuit as claimed in claim 13, wherein the binary logic circuit is configured to left-shift the second intermediate interpolated result by 8 bits and to add a numerical constant of 32 to generate the third intermediate interpolated result.

17. The binary logic circuit as claimed in claim 13, wherein the binary logic circuit is configured to generate the second intermediate interpolated result as: (i) the first intermediate interpolated result C2 when the interpolated result P is not to be compatible with an sRGB colour space; (ii) the summation of the first intermediate interpolated result C2 and a numerical constant when the interpolated result P is to be compatible with an sRGB colour space.

18. A method of using a binary logic circuit to interpolate between two endpoint values E0 and E1 for generating an interpolated result P, the values E0 and E1 being formed from low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the method comprising: performing an interpolation between the colour endpoint values C0 and C1 to generate a first intermediate interpolated result C2; determining the interpolated result P such that the interpolated result P satisfies the equation P=└((C2<<8)+C2+32)/64┘, or satisfies the equation P=└((C2<<8)+128·64+32)/64┘.

19. The method as claimed in claim 18, wherein the interpolation calculation between the two endpoint values E0 and E1 is specified such that p=└(E0·(64−i)+E1·i+32)/64┘, where p is equal to the interpolated result P, and i is a weighting index.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 for generating an interpolated result P, the values E0 and E1 being formed from low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the binary logic circuit being configured to: perform an interpolation between the colour endpoint values C0 and C1 to generate a first intermediate interpolated result C2; and determine the interpolated result P such that the interpolated result P satisfies the equation P=└((C2<<8)+C2+32)/64┘, or satisfies the equation P=└((C2<<8)+128·64+32)/64┘.