Transient Fault Detection in Memory Using Dynamic Bist

1. A self-test circuit, comprising: a counter clocked by a fault indication output by an error correction code (ECC) decoder; and a controller activated by a fault interrupt signal asserted by the ECC decoder and configured, when activated, to iteratively: read first data from a memory location that is indicated by the ECC decoder to be associated with a data storage fault; cause an inverted version of the first data to be written back to the memory location; read second data from the memory location after the inverted version of the first data is written back to the memory location; report the data storage fault as a transient fault to a safety subsystem when the second data has an expected value; and report the data storage fault as a permanent fault to the safety subsystem when the second data does not have the expected value and an output of the counter reaches a threshold value, wherein the controller is deactivated when the data storage fault is reported as a transient fault or as a permanent fault to the safety subsystem.

2. The self-test circuit of claim 1, wherein the controller is further configured to: receive a fault signature from the ECC decoder, wherein the fault signature is received when the fault interrupt signal is asserted and comprises a memory device identifier, and an address of the memory location that is indicated as being associated with the data storage fault.

3. The self-test circuit of claim 2, wherein the fault signature further comprises an ECC corresponding to the fault interrupt signal.

4. The self-test circuit of claim 1, wherein the safety subsystem is provided in an autonomously operated vehicle and is operationally isolated from a processing circuit that comprises a memory device that includes the memory location.

5. The self-test circuit of claim 1, wherein incoming access requests directed to a memory device that includes the memory location are halted while the controller is activated.

6. The self-test circuit of claim 1, wherein the threshold value is configured by the safety subsystem.

7. The self-test circuit of claim 1, wherein the threshold value corresponds to a number of data reads or data writes that ensures that a transient fault is cleared before the data storage fault is reported as a transient fault or as a permanent fault to the safety subsystem.

8. A method for testing memory using a controller, comprising: activating the controller when a fault interrupt signal is asserted by an error correction code (ECC) decoder; and while the controller is activated, iteratively: reading first data from a memory location that is indicated by the ECC decoder to be associated with a data storage fault; causing an inverted version of the first data to be written back to the memory location; reading second data from the memory location after the inverted version of the first data is written back to the memory location; reporting the data storage fault as a transient fault to a safety subsystem when the second data has an expected value; and reporting the data storage fault as a permanent fault to the safety subsystem after a threshold number of iterations has been executed in which the second data does not have the expected value, wherein the controller is deactivated when the data storage fault is reported as a transient fault or as a permanent fault to the safety subsystem.

9. The method of claim 8, further comprising: receiving a fault signature from the ECC decoder, wherein the fault signature is received when the fault interrupt signal is asserted and comprises a memory device identifier, and an address of the memory location that is indicated as being associated with the data storage fault.

10. The method of claim 9, wherein the fault signature further comprises an ECC corresponding to the fault interrupt signal.

11. The method of claim 8, wherein the safety subsystem is provided in an autonomously operated vehicle and is operationally isolated from a processing circuit that comprises a memory device that includes the memory location.

12. The method of claim 8, wherein incoming access requests directed to a memory device that includes the memory location are halted while the controller is activated.

13. The method of claim 8, wherein the threshold number is configured by the safety subsystem.

14. The method of claim 8, wherein the threshold number of iterations corresponds to a number of data reads or data writes that ensures that a transient fault is cleared before the data storage fault is reported as a transient fault or as a permanent fault to the safety subsystem.

15. A processor-readable storage medium comprising code that, when executed by a controller in a processing circuit, causes the processing circuit to: activate the controller when a fault interrupt signal is asserted by an error correction code (ECC) decoder; and while the controller is activated, iteratively: read first data from a memory location that is indicated by the ECC decoder to be associated with a data storage fault; cause an inverted version of the first data to be written back to the memory location; read second data from the memory location after the inverted version of the first data is written back to the memory location; report the data storage fault as a transient fault to a safety subsystem when the second data has an expected value; and report the data storage fault as a permanent fault to the safety subsystem after a threshold number of iterations has been executed in which the second data does not have the expected value, wherein the controller is deactivated when the data storage fault is reported as a transient fault or as a permanent fault to the safety subsystem.

16. The processor-readable storage medium of claim 15, wherein the code further causes the processing circuit to: receive a fault signature from the ECC decoder, wherein the fault signature is received when the fault interrupt signal is asserted and comprises a memory device identifier, and an address of the memory location that is indicated as being associated with the data storage fault.

17. The processor-readable storage medium of claim 16, wherein the fault signature further comprises an ECC corresponding to the fault interrupt signal.

18. The processor-readable storage medium of claim 15, wherein the safety subsystem is provided in an autonomously operated vehicle and is operationally isolated from a processing circuit that comprises a memory device that includes the memory location.

19. The processor-readable storage medium of claim 15, wherein threshold number is configured by the safety subsystem.

20. The processor-readable storage medium of claim 15, wherein the threshold value corresponds to a number of data reads or data writes that ensures that a transient fault is cleared before the data storage fault is reported as a transient fault or as a permanent fault to the safety subsystem.