Die-Based Rank Management

1. An apparatus comprising: a memory device comprising: a link controller configured to receive a memory request from a host; a memory controller configured to receive, via an interconnect, the memory request from the link controller and generate, based on the memory request, a memory command; memory organized into multiple ranks; physical control logic coupling the memory controller to the memory organized into the multiple ranks; and rank mapping logic implemented by the memory controller and coupled with a storage element, the rank mapping logic configured to: determine that a memory die of one of the multiple ranks is not functional to store data; determine information that indicates correlations of rank selections of memory addresses to ranks of the multiple ranks of the memory device by remapping a rank selection from the rank that includes the memory die that is not functional to another rank of the multiple ranks; store, to the storage element of the memory controller, the information that indicates the correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device; determine that a rank selection of an address of the memory command provided by the memory controller corresponds to the rank selection that is remapped from the rank that includes the memory die that is not functional to the other rank of the multiple ranks; and cause, based on the information, the memory controller to redirect the memory command from the rank that includes the memory die that is not functional to the other rank of the multiple ranks to enable access to the memory device.

2. The apparatus of claim 1, wherein the rank mapping logic of the memory controller is further configured to determine the rank of the multiple ranks that corresponds to the rank selection based on the information.

3. The apparatus of claim 1, wherein the information of the storage element comprises a table that indicates correlations of rank selections available through memory addresses to respective ones of the multiple ranks of the memory device, including the correlation of the rank selection of the memory address of the received memory command to the rank of the multiple ranks of the memory device.

4. The apparatus of claim 1, wherein: the memory of the memory device comprises multiple memory dies that are organized into the multiple ranks.

5. The apparatus of claim 1, wherein the rank mapping logic of the memory controller is further configured to determine that the memory die of the memory device is not functional to store data during fabrication, production, or testing of the memory device.

6. The apparatus of claim 1, wherein the rank mapping logic of the memory controller is further configured to: determine the correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device during fabrication, production, or testing of the memory device; or store the information indicating correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device to the storage element during the fabrication, the production, or the testing of the memory device.

7. The apparatus of claim 1, further comprising a fuse circuit operably coupled with the rank mapping logic and configured to maintain state information indicating that the memory die of the memory device is not functional to store data.

8. The apparatus of claim 1, wherein the rank mapping logic of the memory controller is further configured to disable the memory die of the memory device that is not functional to store data.

9. The apparatus of claim 1, wherein the rank mapping logic of the memory controller is further configured to determine that the memory die of the memory device is not functional to store data following a power-up or reset of the memory device.

10. The apparatus of claim 1, wherein the rank mapping logic of the memory controller is further configured to: determine the correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device following power-up or reset of the memory device; or store the information indicating the correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device to the storage element following the power-up or reset of the memory device.

11. The apparatus of claim 1, wherein: the rank mapping logic of the memory controller is further configured to determine the correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device; and the ranks of the multiple ranks comprise available ranks that memory dies of the memory device that are functional.

12. The apparatus of claim 1, wherein the storage element configured to store the information comprises a nonvolatile memory circuit.

13. The apparatus of claim 12, wherein the rank mapping logic of the memory controller comprises the nonvolatile memory circuit.

14. The apparatus of claim 1, wherein the memory controller comprises: the rank mapping logic and the storage element that stores the information that indicates the correlations of the rank selections of the memory addresses to the ranks of the multiple ranks of the memory device.

15. The apparatus of claim 1, wherein the memory device comprises a center controller that is communicatively coupled with the link controller and the memory controller of the memory device.

16. The apparatus of claim 1, wherein: the memory device comprises multiple memory controllers that include respective instances of the rank mapping logic; and each of the multiple memory controllers is configured to access a respective subset of the memory dies of the memory and includes a respective storage element configured to store information that correlates the rank selections of the memory addresses with ranks comprising one or more memory dies of the respective subset of the memory dies.

17. The apparatus of claim 1, wherein the apparatus comprises a multiple die package (MDP) that comprises the memory and the memory controller with the rank mapping logic.

18. An apparatus comprising: a memory device including: memory dies organized into multiple ranks; a memory controller configured to receive, via an interconnect and from a host, a memory request and generate, based on the memory request, a memory command; and rank mapping logic implemented by the memory controller and coupled with a storage element, the rank mapping logic configured to: determine that a memory die of one of the ranks of the multiple ranks is not functional to store data; determine information that indicates a mapping of memory address rank selections to respective ranks of the multiple ranks by remapping a rank selection from the rank that includes the memory die that is not functional to another rank of the multiple ranks; store, to the storage element of the memory controller, the information that indicates the mapping of the memory address rank selections to the respective ranks of the multiple ranks of the memory device; determine that a rank selection of an address of the memory command provided by the memory controller corresponds to the rank selection that is remapped from the rank that includes the memory die that is not functional to the other rank of the multiple ranks; and cause, based on the information indicative of the mapping, the memory controller to redirect the memory command from the rank that includes the memory die that is not functional to the other rank of the multiple ranks to enable access to the memory device.

19. The apparatus of claim 18, wherein the information indicative of the mapping that is stored by the storage element comprises a table that indicates the mapping of the memory address rank selections to the respective ranks of the multiple ranks to provide the mapped ranks of the memory device.

20. The apparatus of claim 18, wherein the rank selection logic of the memory controller is further configured to: determine the mapping of the memory address rank selections to the respective ranks of the multiple ranks during fabrication, production, or testing of the memory device; or store the mapping of the memory address rank selections to the respective ranks of the multiple ranks in the storage element during the fabrication, the production, or the testing of the memory device.

21. The apparatus of claim 18, wherein at least one of the memory dies that is not functional to store data is not organized into the multiple ranks of the memory device.

22. The apparatus of claim 18, wherein the rank mapping logic of the memory controller is further configured to determine that the memory die is not functional to store data during fabrication, production, or testing of the memory device.

23. The apparatus of claim 18, wherein the rank mapping logic of the memory controller is further configured to determine that the memory die is not functional to store data following a power-up or reset of the memory device.

24. The apparatus of claim 18, wherein the rank mapping logic of the memory controller is further configured to: determine the mapping of the memory address rank selections to the respective ranks of the multiple ranks following a power-up or reset of the memory device; or store the information indicating the mapping of the memory address rank selections to the respective ranks of the multiple ranks in the storage element following the power-up or reset of the memory device.

25. The apparatus of claim 18, wherein the rank mapping logic of the memory controller is further configured to: determine the memory dies of the memory device that are functional to store data; and form the respective ranks of the multiple ranks from the memory dies that are determined to be functional to store data.

26. The apparatus of claim 18, wherein: the memory device comprises multiple memory controllers that include respective instances of the rank mapping logic; and each of the multiple memory controllers is configured to access a respective subset of the memory dies of the memory device and comprises a respective storage element storing a mapping of the memory address rank selections to a respective set of ranks accessible by each of the multiple memory controllers.

27. The apparatus of claim 18, wherein the memory device comprises a multiple die package (MDP) comprising the memory dies and the memory controller with the rank mapping logic.

28. An apparatus comprising: a storage element configured to store a mapping of rank selections of memory addresses to corresponding ranks of multiple ranks of a memory device as mapped ranks; a memory controller configured to receive, from a host, a memory request and generate, based on the memory request, a memory command; an interface operably coupled to an interconnect through which the multiple ranks of the memory device are accessible; and rank mapping logic implemented by the memory controller and coupled with the storage element and the interface, the rank mapping logic configured to: determine, via the interface, that a memory die of one of the ranks of the multiple ranks of the memory device is not functional to store data; generate the mapping of the rank selections of memory addresses to the corresponding ranks of the multiple ranks by remapping a rank selection from the rank that includes the memory die that is not functional to another rank of the multiple ranks; store, to the storage element, the mapping of the rank selections of the memory addresses to the corresponding ranks of the multiple ranks of the memory device; determine that a memory address rank selection of the memory command provided by the memory controller corresponds to the rank selection remapped from the rank that includes the memory die that is not functional to the other rank of the multiple ranks; and cause, based on the mapping, the memory controller to redirect the memory command from the rank that includes the memory die that is not functional to the other rank of the multiple ranks to enable access to the memory device.

29. The apparatus of claim 28, wherein the mapping is stored in the storage element as a table of the mapped ranks that correspond to the rank selections of the memory addresses.

30. The apparatus of claim 28, wherein the memory device comprises multiple memory dies and the rank mapping logic of the memory controller is further configured to: generate the mapping in response to determining that the memory die is not functional to store data, the memory die that is not functional to store data being excluded from the multiple ranks of the memory device.

31. The apparatus of claim 30, wherein the rank mapping logic of the memory controller is further configured to: generate the mapping in association with testing, a power-up, or a reset of the memory device; or store the mapping to the storage element following the testing, the power-up, or the reset of the memory device.

32. The apparatus of claim 28, wherein the rank mapping logic of the memory controller is further configured to: determine that one or more of the multiple memory dies of the memory device are functional to store data; and generate the multiple ranks of the mapping from the one or more of the multiple memory dies that are determined to be functional to store data.

33. The apparatus of claim 28, wherein the storage element comprises a nonvolatile memory circuit.

34. The apparatus of claim 28, wherein the storage element is embodied as part of the rank mapping logic of the memory controller of the apparatus.

35. The apparatus of claim 28, wherein: the apparatus comprises multiple memory controllers that include respective instances of the rank mapping logic; and each of the multiple memory controllers is configured to access a respective set of ranks of the memory device and comprises a respective storage element storing a mapping of the memory address rank selections to the respective set of ranks accessible by the controller.

36. A method comprising: determining, by rank mapping logic of a memory controller operably coupled to multiple memory dies of a memory device organized into multiple ranks, that a memory die of one of the ranks of the multiple ranks is not functional to store data; determining a mapping of rank selections of memory addresses to corresponding ranks of the multiple ranks by remapping a rank selection from the rank that includes the memory die that is not functional to another rank of the multiple ranks; storing, to a storage element of the memory controller, the mapping of the rank selections of memory addresses to the corresponding ranks of the multiple ranks of the memory device; receiving a memory command from a host that comprises a memory address with a rank selection for one rank of multiple ranks of the memory device; determining, based on the mapping, that the rank selection of the memory command corresponds to the rank selection that is remapped from the rank that includes the memory die that is not functional to the other rank of the multiple ranks and causing, based on the mapping, the memory controller to redirect the memory command from the rank that includes the memory die that is not functional to the other rank of the multiple ranks to enable access to the memory device.

37. The method of claim 36, wherein determining that the rank selection of the memory command corresponds to the rank selection that is remapped further comprises accessing the storage element that stores the mapping of the rank selections of the memory addresses to the corresponding ranks of the multiple ranks of the memory device.

38. The method of claim 36, wherein the memory device comprises a number of physical ranks that is greater than a number of the multiple ranks that are accessible through the rank selection of the memory address or other rank selections of other memory addresses.

39. The method of claim 36, wherein: the mapping comprises a sequence of the multiple ranks that does not linearly correspond with a sequence of the rank selections.

40. A method comprising: determining that one or more memory dies of a rank of a memory device are not functional to store data; correlating rank selections accessible through memory addressing of the memory device to another rank of multiple ranks of the memory device by remapping a rank selection that includes the one or more memory dies that are not functional to another rank of the other ranks of the memory device; storing information that indicates the correlation of the rank selections to the other ranks of the memory device to a storage element associated with a memory controller of the memory device; receiving, by the memory controller, a memory command from a host that comprises a memory address with a rank selection for one rank of multiple ranks of the memory device; determining, based on the information, that the rank selection of the memory command corresponds to the rank selection that is remapped from the rank that includes the one or more memory dies that are not functional to the other rank of the multiple ranks; and redirecting, by the memory controller, the memory command from the rank that includes the memory die that is not functional to the other rank of the multiple ranks to enable access to the memory device.

41. The method of claim 40, further comprising determining that one or more other memory dies of the other ranks of the multiple ranks of the memory device are functional to store data.

42. The method of claim 40, wherein the determining, the correlating, or the storing is performed during fabrication, production, or testing of the memory device.

43. The method of claim 40, wherein the determining, the correlating, or the storing is performed following a power-up or reset of the memory device.

44. The method of claim 40, wherein an ordering or sequence of the rank selections does not correspond linearly with an ordering or sequence of the other ranks of the multiple ranks of the memory device that are functional to store data.

45. The method of claim 40, wherein the memory device comprises a number of physical ranks that include the rank and other ranks that is greater than a number of the rank selections accessible through memory addressing of the memory device.

46. The method of claim 40, wherein the corresponding is performed such that the rank that is not functional is excluded from the other ranks and is not accessible using the rank selections accessible through memory addressing of the memory device.