Adaptive System Probe Action to Minimize Input/Output Dirty Data Transfers

1. A system comprising: a processor; a memory configured to store data; a cache configured to store a portion of the data stored in the memory for execution by the processor; and a cache coherence controller comprising a cache line history, the cache coherence controller configured to: identify a cache line associated with a direct memory access request, the direct memory access request associated with an operation involving the data; and responsive to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache, the dirty data transfer record including information that indicates whether a dirty transfer was triggered by a previous request for the cache line.

2. The system of claim 1, wherein the cache coherence controller is configured to selectively send the probe to the cache based on a state of the cache line, the state of the cache line comprising a modified state, an exclusive state, a shared state, or an invalid state.

3. The system of claim 2, wherein the cache coherence controller is further configured to, in response to determining that the state of the cache line is the exclusive state, send the probe to the cache to invalidate the cache line.

4. The system of claim 2, wherein the cache coherence controller is further configured to, in response to determining that the state of the cache line is the shared state, send the probe to convert the state of the cache line from a dirty shared state to a clean shared state.

5. The system of claim 1, wherein the processor comprises a first core and a second core, and wherein the cache comprises a first cache corresponding to the first core and a second cache corresponding to the second core.

6. The system of claim 5, wherein the first cache stores the portion of the data in the cache line.

7. The system of claim 5, wherein the first core transfers the portion of the data from the first cache to the second cache.

8. The system of claim 5, wherein the first core modifies the portion of the data to create a new portion of the data that is different from the portion of the data.

9. The system of claim 8, wherein the cache coherence controller is further configured to update the cache line history to reflect that the portion of the data was modified before being transferred to the second cache.

10. The system of claim 1, wherein the operation involving the data comprises an input or output operation.

11. The system of claim 1, wherein the cache coherence controller is configured to selectively send the probe to the cache by sending the probe to the cache if the information in the dirty data transfer record indicates that the dirty transfer was triggered by the previous request for the cache line.

12. The system of claim 1, wherein the cache coherence controller is configured to selectively send the probe to the cache by not sending the probe to the cache if the information in the dirty data transfer record indicates that the dirty transfer was not triggered by the previous request for the cache line.

13. A cache coherence controller comprising: a memory configured to store a cache line history; and a hardware circuitry configured to: identify a cache line associated with a direct memory access request, the direct memory access request associated with an operation involving data stored in a cache; and responsive to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache, the dirty data transfer record including information that identifies whether a dirty transfer was triggered by a previous request for the cache line.

14. The cache coherence controller of claim 13, wherein hardware circuitry comprises the memory.

15. The cache coherence controller of claim 13, wherein the hardware circuitry is configured to selectively send the probe to the cache based on a state, the state comprising a modified state, an exclusive state, a shared state, or an invalid state.

16. The cache coherence controller of claim 15, wherein the hardware circuitry is further configured to, in response to determining that the state of the cache line is the shared state, send the probe to convert the state of the cache line from a dirty shared state to a clean shared state.

17. The cache coherence controller of claim 13, wherein the hardware circuitry is further configured to update the cache line history to reflect that a portion of the data was modified before being transferred to the cache.

18. The cache coherence controller of claim 13, wherein the operation involving the data comprises an input operation or an output operation.

19. A method comprising: detecting, by a cache coherence controller, a direct memory access request from a direct memory access engine of an input/output device, the direct memory access request associated with an input/output operation performed by the input/output device; and responsive to detecting the direct memory access request, selectively executing, by the cache coherence controller, an adaptive algorithm to ensure coherency of data between a plurality of caches and a memory, the data associated with the input/output operation, wherein the cache coherence controller selectively executes the adaptive algorithm based on a dirty data transfer record that includes information regarding previous requests to the caches.

20. The method of claim 19, wherein selectively executing, by the cache coherence controller, the adaptive algorithm comprises executing, by the cache coherence controller, the adaptive algorithm in response to the data being associated with a dirty data transfer from a first cache of the plurality of caches to a second cache of the plurality of caches.