Disaggregated Entropy Services for Microelectronic Assemblies

1. A microelectronic assembly, comprising: a first plurality of integrated circuit (IC) dies in a first level, each one of the first plurality of IC dies having respective first physical unclonable function (PUF) circuits, each one of the first PUF circuits configured to generate a respective unique first PUF identifier; a second IC die having a second PUF circuit and a security circuit, the second PUF circuit configured to generate a unique second PUF identifier, the security circuit configured to be an entropy source; a second plurality of IC dies in a second level, the second level not coplanar with the first level, the first level and the second level being coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects; and conductive pathways between the first plurality of IC dies and the second IC die for communication between the first PUF circuits and the second PUF circuit, the conductive pathways comprising a portion of the interconnects, wherein: each one of the first PUF circuits is further configured to: identify the second PUF circuit by the second PUF identifier, and generate a first cryptographic key encrypting a request to the security circuit for entropy, and the second PUF circuit is configured to: identify each one of the first PUF circuits by the respective first PUF identifiers, and generate a second cryptographic key encrypting a response from the security circuit to the request.

2. The microelectronic assembly of claim 1, wherein: the second IC die is in the first level, and a portion of the conductive pathways is through the second plurality of IC dies in the second level.

3. The microelectronic assembly of claim 1, further comprising a redistribution layer between the first level and the second level, wherein the redistribution layer is coupled to the first level and the second level with the interconnects.

4. The microelectronic assembly of claim 3, wherein: the second IC die is in the first level, and a portion of the conductive pathways is through the redistribution layer.

5. The microelectronic assembly of claim 3, wherein: the second IC die is in the second level, and a portion of the conductive pathways is through the redistribution layer.

6. The microelectronic assembly of claim 1, wherein the entropy comprises a sequence of at least one of random numbers and random bits.

7. The microelectronic assembly of claim 1, wherein any one of the conductive pathways is through a first metallization stack of one of the first plurality of IC dies, a second metallization stack of the second IC die and the portion of the interconnects.

8. An IC package, comprising: a first IC die comprising a first PUF circuit to generate a first PUF identifier and a first cryptographic key; a second IC die comprising a second PUF circuit to generate a second PUF identifier and a second cryptographic key, the second IC die further comprising a digital random number generator circuit to generate random numbers or random bits; a third IC die; and a package substrate coupled at least to the third IC die, wherein: the first IC die is in a first level, the third IC die is in a second level not coplanar with the first level, the first level and the second level are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and communication between the first PUF circuit and the second PUF circuit is configured to be through a conductive pathway, the conductive pathway comprising a portion of the interconnects and the communication being encrypted using the first PUF identifier, the first cryptographic key, the second PUF identifier and the second cryptographic key.

9. The IC package of claim 8, wherein the second IC die is in the first level.

10. The IC package of claim 8, wherein the second IC die is in the second level.

11. The IC package of claim 10, wherein the first IC die in the first level is directly over the second IC die in the second level.

12. The IC package of claim 8, wherein a portion of the conductive pathway is through the third IC die in the second level.

13. The IC package of claim 8, further comprising a redistribution layer between the first level and the second level, wherein a portion of the conductive pathway is through the redistribution layer.

14. An IC device, comprising: a security circuit; and a first PUF circuit configured to generate a first PUF identifier and a first cryptographic key, wherein: the IC device is coupled to a plurality of IC dies having respective second PUF circuits, wherein one of the plurality of IC dies is configured to generate a second PUF identifier and second cryptographic key, the IC device and the plurality of IC dies are coupled together in an IC package, the first PUF circuit and the second PUF circuits are configured to communicate securely with each other through conductive pathways in the IC package, wherein a communication through the conductive pathways in the IC package is encrypted using the first PUF identifier, the first cryptographic key, the second PUF identifier, and the second cryptographic key, the security circuit is configured to provide entropy services to the plurality of IC dies, and the entropy services comprise providing a sequence of random numbers or random bits.

15. The IC device of claim 14, wherein the conductive pathways comprise interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.

16. The IC device of claim 14, wherein the first PUF identifier is to identify the IC device, and the second PUF identifier is to identify the one of the plurality of IC dies.

17. The IC device of claim 14, wherein the second PUF circuit comprises a logic circuit, a system monitor, a controller and a PUF array.

18. The IC device of claim 17, wherein the PUF array comprises an array of ring oscillators.

19. The IC device of claim 14, wherein the security circuit comprises a digital random number generator circuit, comprising a hardware entropy source, a hardware conditioner, and at least one of a hardware deterministic random bit generator and a hardware nondeterministic random bit generator.

20. The IC device of claim 19, wherein: the hardware entropy source is configured to produce random bits from a nondeterministic hardware process, the hardware conditioner is configured to distill the random bits into high-quality nondeterministic random numbers, the hardware deterministic random bit generator is configured to generate random numbers seeded from the hardware conditioner, and the hardware nondeterministic random bit generator is configured to provide random seeds generated from the hardware conditioner.