Sorted Change Log for Physical Page Table Compression

1. A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive, from a host system, a write command that is associated with data and a logical address; write, in response to the write command, the data to a physical address; store, based at least in part on the data being written to the physical address, a mapping at a location of a change log buffer, wherein the mapping indicates a relationship between the logical address and the physical address; compare a value of the logical address with values of logical addresses of other mappings stored in the change log buffer, wherein the location of the mapping that is stored in the change log buffer is based at least in part on comparing the value of the logical address with the values of logical addresses of the other mappings stored in the change log buffer; identify a set of sequentially-indexed logical addresses stored in the change log buffer based at least in part on comparing the value of the logical address relative to the values of logical addresses of the other mappings stored in the change log buffer; generate, based at least in part on identifying the set of sequentially-indexed logical addresses stored in the change log buffer, a compressed entry in a logical-to-physical table for a set of mappings stored in the change log buffer, the set of mappings comprising the set of sequentially-indexed logical addresses; and write, to a non-volatile memory device, a portion of the logical-to-physical table, wherein the portion of the logical-to-physical table comprises the compressed entry for the set of sequentially-indexed logical addresses.

2. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine, based at least in part on storing the mapping in the change log buffer, that the set of mappings comprises the set of sequentially-indexed logical addresses.

3. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine that a quantity of logical addresses in the set of sequentially-indexed logical addresses satisfies a threshold, wherein the compressed entry in the logical-to-physical table is generated based at least in part on the quantity of logical addresses satisfying the threshold.

4. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine the logical address of the mapping is between a second logical address of a second mapping stored in a second location of the change log buffer and a third logical address of a third mapping stored in a third location of the change log buffer; and identify the location based at least in part on the second location and the third location, wherein the mapping is stored at the location based at least in part on identifying the location.

5. The memory system of claim 4, wherein, to determine the logical address is between the second logical address and the third logical address, the processing circuitry is further configured to cause the memory system to: identify, based at least in part on the comparing, that the second mapping comprises the second logical address that is less than the logical address and that the third mapping comprises the third logical address that is greater than the logical address.

6. The memory system of claim 4, wherein the processing circuitry is further configured to cause the memory system to: receive, from the host system, a second write command that is associated with second data and a fourth logical address; write, in response to the second write command, the second data to a fourth physical address, wherein a fourth mapping indicates a relationship between the fourth logical address and the fourth physical address based at least in part on the second data being written to the fourth physical address; determine the fourth logical address of the fourth mapping is between the logical address of the mapping and the third logical address of the third mapping; and store the fourth mapping at a fourth location of the change log buffer, the fourth location being positioned between the location and the third location based at least in part on the fourth logical address being between the logical address and the third logical address.

7. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: load, from the non-volatile memory device, the portion of the logical-to-physical table; and modify the portion of the logical-to-physical table based at least in part on mappings stored in the change log buffer, the mappings comprising the set of mappings and a second set of mappings, wherein writing, to the non-volatile memory device, the portion of the logical-to-physical table is based at least in part on modifying the portion of the logical-to-physical table.

8. The memory system of claim 7, wherein the logical-to-physical table comprises a first-level table and a second-level table, and wherein, to modify the portion of the logical-to-physical table, the processing circuitry is further configured to cause the memory system to: modify one or more entries in the first-level table based at least in part on the second set of mappings; and modify an entry in the second-level table based at least in part on the compressed entry, wherein the entry in the second-level table corresponds to a set of entries in the first-level table that encompasses the set of sequentially-indexed logical addresses.

9. The memory system of claim 7, wherein the second set of mappings comprises non-sequentially-indexed logical addresses that are excluded from the set of sequentially-indexed logical addresses.

10. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: generate a second compressed entry in the logical-to-physical table for a second set of mappings stored in the change log buffer, the second set of mappings comprising a second set of sequentially-indexed logical addresses stored in the change log buffer.

11. The memory system of claim 1, wherein: the change log buffer comprises a plurality of locations for storing mappings between logical addresses and physical addresses, the plurality of locations comprising the location, and the set of mappings is stored at a set of locations of the plurality of locations, the set of locations comprising the location.

12. The memory system of claim 1, wherein the change log buffer comprises a plurality of locations for temporarily storing mappings between logical addresses and physical addresses based at least in part on the data being written to physical addresses of the non-volatile memory device.

13. The memory system of claim 1, further comprising: a change log management circuit configured to order, based at least in part on storing the mapping in the change log buffer, mappings of the change log buffer based at least in part on the logical address of the mapping and the logical addresses of the other mappings, wherein generating the compressed entry is based at least in part on ordering the mappings.

14. A non-transitory, computer-readable medium storing code comprising instructions which, when executed by a processing circuitry of an electronic device, cause the electronic device to: receive, from a host system, a write command that is associated with data and a logical address; write, in response to the write command, the data to a physical address; store, based at least in part on the data being written to the physical address, a mapping at a location of a change log buffer, wherein the mapping indicates a relationship between the logical address and the physical address; compare a value of the logical address with values of logical addresses of other mappings stored in the change log buffer, and wherein the location of the mapping that is stored in the change log buffer is based at least in part on comparing the value of the logical address with the values of logical addresses of the other mappings stored in the change log buffer; identify a set of sequentially-indexed logical addresses stored in the change log buffer based at least in part on comparing the value of the logical address relative to the values of logical addresses of the other mappings stored in the change log buffer; generate, based at least in part on identifying the set of sequentially-indexed logical addresses stored in the change log buffer, a compressed entry in a logical-to-physical table for a set of mappings stored in the change log buffer, the set of mappings comprising the set of sequentially-indexed logical addresses; and write, to a non-volatile memory device, a portion of the logical-to-physical table, wherein the portion of the logical-to-physical table comprises the compressed entry for the set of sequentially-indexed logical addresses.

15. The non-transitory, computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the electronic device to: determine, based at least in part on storing the mapping in the change log buffer, that the set of mappings comprises the set of sequentially-indexed logical addresses.

16. The non-transitory, computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the electronic device to: determine that a quantity of logical addresses in the set of sequentially-indexed logical addresses satisfies a threshold, wherein the compressed entry in the logical-to-physical table is generated based at least in part on the quantity of logical addresses satisfying the threshold.

17. The non-transitory, computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the electronic device to: determine the logical address of the mapping is between a second logical address of a second mapping stored in a second location of the change log buffer and a third logical address of a third mapping stored in a third location of the change log buffer; and identify the location based at least in part on the second location and the third location, wherein the mapping is stored at the location based at least in part on identifying the location.

18. The non-transitory, computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the electronic device to: load, from the non-volatile memory device, the portion of the logical-to-physical table; and modify the portion of the logical-to-physical table based at least in part on mappings stored in the change log buffer, the mappings comprising the set of mappings and a second set of mappings, wherein writing, to the non-volatile memory device, the portion of the logical-to-physical table is based at least in part on modifying the portion of the logical-to-physical table.

19. The non-transitory, computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the electronic device to: generate a second entry in the logical-to-physical table for a second set of mappings stored in the change log buffer, the second set of mappings comprising a second set of sequentially-indexed logical addresses stored in the change log buffer.

20. The non-transitory, computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the electronic device to: order, based at least in part on storing the mapping in the change log buffer, mappings of the change log buffer based at least in part on the logical address of the mapping and the logical addresses of the other mappings, wherein generating the compressed entry is based at least in part on ordering the mappings.

21. A method, comprising: receiving, from a host system, a write command that is associated with data and a logical address; writing, in response to the write command, the data to a physical address; storing, based at least in part on the data being written to the physical address, a mapping at a location of a change log buffer, wherein the mapping indicates a relationship between the logical address and the physical address; comparing a value of the logical address with values of logical addresses of other mappings stored in the change log buffer, and wherein the location of the mapping that is stored in the change log buffer is based at least in part on comparing the value of the logical address with the values of logical addresses of the other mappings stored in the change log buffer; identifying a set of sequentially-indexed logical addresses stored in the change log buffer based at least in part on comparing the value of the logical address relative to the values of logical addresses of the other mappings stored in the change log buffer; generating, based at least in part on identifying the set of sequentially-indexed logical addresses stored in the change log buffer, a compressed entry in a logical-to-physical table for a set of mappings stored in the change log buffer, the set of mappings comprising the set of sequentially-indexed logical addresses; and writing, to a non-volatile memory device, a portion of the logical-to-physical table, wherein the portion of the logical-to-physical table comprises the compressed entry for the set of sequentially-indexed logical addresses.

22. The method of claim 21, further comprising: determining, based at least in part on storing the mapping in the change log buffer, that the set of mappings comprises the set of sequentially-indexed logical addresses.

23. The method of claim 21, further comprising: determining that a quantity of logical addresses in the set of sequentially-indexed logical addresses satisfies a threshold, wherein the compressed entry in the logical-to-physical table is generated based at least in part on the quantity of logical addresses satisfying the threshold.

24. The method of claim 21, further comprising: determining the logical address of the mapping is between a second logical address of a second mapping stored in a second location of the change log buffer and a third logical address of a third mapping stored in a third location of the change log buffer; and identifying the location based at least in part on the second location and the third location, wherein the mapping is stored at the location based at least in part on identifying the location.

25. The method of claim 21, further comprising: ordering, by a change log management circuit and based at least in part on storing the mapping in the change log buffer, mappings of the change log buffer based at least in part on the logical address of the mapping and the logical addresses of the other mappings, wherein generating the compressed entry is based at least in part on ordering the mappings.