Methods of Designing Layout of Semiconductor Device and Methods for Manufacturing Semiconductor Device Using the Same

1. A method of designing a layout of a semiconductor device, comprising: preparing a standard cell library comprising information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library, wherein the common pattern region comprises a common active pattern; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells or to overlap the common pattern region based on a width of the common active pattern.

2. The method of claim 1, wherein, in the arranging the standard cells, the common pattern region is between the at least one pair of adjacent ones of the standard cells.

3. The method of claim 1, wherein, in the arranging the standard cells, the at least one pair of adjacent ones of the standard cells contact each other.

4. The method of claim 1, wherein the common active pattern is connected to a cell pattern in at least one of the standard cells, and wherein the arranging the standard cells is based on a comparison between the width of the common active pattern and a width of the cell pattern.

5. The method of claim 1, wherein the standard cells comprise a first portion that comprises a first active pattern having a first width and a second portion that comprises a second active pattern having a second width that is different from the first width, wherein the width of the common active pattern is equal to the first width, and wherein the common pattern region overlaps the first portion of the standard cells.

6. The method of claim 1, wherein a width of the common pattern region is smaller than a width of at least one of the standard cells.