Standard Cell Mulilayer Semiconductor Integrated Circuit Device

1. A two-terminal circuit that is formed in a multilayer semiconductor integrated circuit device so as to extend over a plurality of layers thereof, including a plurality of signal paths, each of which is laid at one or more of the plurality of layers to connect two terminals of the circuit, and includes a restricted part at each of the one or more layers, the restricted part being formed either in (a) a connected state for permitting transmission of a signal at the restricted part of the signal path or in (b) a disconnected state for preventing transmission of a signal at the restricted part of the signal path, wherein each of the plurality of layers includes at least different one of the plurality of signal paths that is laid thereat.

2. A two-terminal circuit according to claim 1 , wherein each signal path is laid at and passes through all of the plurality of layers, to connect the two terminals.

3. A two-terminal circuit according to claim 2 , wherein in each signal path, restricted parts in the plurality of layers are formed in one of the following states where (a) restricted parts in all the layers are in the connected state, (b) a restricted part in one layer is in the disconnected state and restricted parts in layers other than the one layer are in the connected state, and (c) restricted parts in two layers are in the connected state and restricted parts in layers other than the two layers are in the connected state.

4. A two-terminal circuit according to claim 2 , wherein each signal path is sequentially laid at and passes through adjacent layers of the plurality of layers, to connect the two terminals.

5. A signal selection circuit, comprising: a plurality of input terminals; a plurality of two-terminal circuits, each of which is a two-terminal circuit defined in claim 1 , and is provided in correspondence with different one of the input terminals, a first terminal of each two-terminal circuit being electrically connected to the corresponding input terminal; and an output terminal that is electrically connected to a second terminal of each two-terminal circuit.

6. A standard cell that is formed in a multilayer semiconductor integrated circuit device, including a two-terminal circuit defined in claim 1 .

7. A standard cell according to claim 6 , comprising: a plurality of input terminals that are electrically connected to an outside of the standard cell; a plurality of two-terminal circuits, each of which is a two-terminal circuit defined in claim 1 , and is provided in correspondence with different one of the input terminals, a first terminal of each two-terminal circuit being electrically connected to the corresponding input terminal; and an output terminal that is electrically connected to a second terminal of each two-terminal circuit, and that is electrically connected to an outside of the standard cell.

8. A standard cell group that includes an input standard cell and an output standard cell, the input standard cell being a standard cell defined in claim 6 , including: a first input terminal that is electrically connected to an outside of the input standard cell; a first two-terminal circuit that is a two-terminal circuit defined in claim 1 , a first terminal thereof being electrically connected to the first input terminal; and a first relay output terminal that is electrically connected to a second terminal of the first two-terminal circuit, and the output standard cell being a standard cell defined in claim 6 , including: a second input terminal that is electrically connected to an outside of the output standard cell; a second two-terminal circuit that is a two-terminal circuit defined in claim 1 , a first terminal thereof being electrically connected to the second input terminal; a first relay input terminal; and an output terminal that is electrically connected to a second terminal of the second two-terminal circuit and to the first relay input terminal, and that is electrically connected to an outside of the output standard cell, wherein when the input standard cell and the output standard cell are placed at predetermined locations, the first relay output terminal and the first relay input terminal are electrically connected to each other.

9. A standard cell group according to claim 8 , further including a relay standard cell that is a standard cell defined in claim 6 , the relay standard cell including: a third input terminal that is electrically connected to an outside of the relay standard cell; a third two-terminal circuit that is a two-terminal circuit defined in claim 1 , a first terminal thereof being electrically connected to the third input terminal; a second relay input terminal; and a second relay output terminal that is electrically connected to a second terminal of the third two-terminal circuit and to the second relay input terminal, wherein when the input standard cell, the output standard cell, and the relay standard cell are placed at predetermined locations, the first relay output terminal and the second relay input terminal are electrically connected to each other, and the second relay output terminal and the first relay input terminal are electrically connected to each other.

10. A standard cell according to claim 6 , further including: one or both of a pull-down circuit and a pull-up circuit; and an output terminal that is electrically connected to a first terminal of the two-terminal circuit, and that is electrically connected to an outside of the standard cell, wherein either the first terminal of the two-terminal circuit is electrically connected to the pull-down circuit and a second terminal of the two-terminal circuit is electrically connected to a power supply, or the first terminal of the two-terminal circuit is electrically connected to the pull-up circuit and the second terminal of the two-terminal circuit is electrically connected to a ground.

11. A standard cell according to claim 6 , further including: one or both of a pull-down circuit and a pull-up circuit; a first input terminal that is electrically connected to an outside of the standard cell; a second input terminal that is electrically connected to an outside of the standard cell; a gate circuit that passes one of (a) a signal that has been inputted into the first input terminal and (b) a signal that has been inputted into the second input terminal, according to a signal obtained from a first terminal of the two-terminal circuit; and an output terminal that outputs the signal that has been passed from the gate circuit, to an outside of the standard cell, wherein either the first terminal of the two-terminal circuit is electrically connected to the pull-down circuit and a second terminal of the two-terminal circuit is electrically connected to a power supply, or the first terminal of the two-terminal circuit is electrically connected to the pull-up circuit and the second terminal of the two-terminal circuit is electrically connected to a ground.

12. A variable delay circuit, comprising: a signal delay circuit that delays an input signal to generate one or more delay signals each having a different delay time; and a signal selection circuit that is a signal selection circuit defined in claim 5 , and includes a plurality of input terminals into which a plurality of signals out of the input signal and the generated delay signals are inputted respectively.

13. A semiconductor integrated circuit device that can execute a plurality of functions, comprising: a two-terminal circuit that is a two-terminal circuit defined in claim 1 ; and a restriction circuit that restricts at least one function identified by a state of the two-terminal circuit, out of the plurality of functions.

14. A semiconductor integrated circuit device in which first information that needs to be concealed from a user is generated, comprising: a two-terminal circuit that is a two-terminal circuit defined in claim 1 ; an encryption circuit that encrypts the first information using key information identified by a state of the two-terminal circuit, to generate second information; and an output circuit that outputs the second information to an outside of the device.

15. A semiconductor integrated circuit device according to claim 14 , further comprising a signal selection circuit that is a signal selection circuit defined in claim 5 and that includes an input terminal in which the first information has been inputted and an input terminal in which the second information has been inputted, wherein the output circuit outputs one of the first information and the second information that is outputted from the signal selection circuit, to an outside of the device.