Smart Retry System That Reduces Wasted Bus Transactions Associated with Master Retries

1. In a computer system including a bus, a master device, a plurality of slave devices and a single arbiter coupled to said bus, said arbiter adapted to regulate access to said bus by said master device and said plurality of slave devices, said arbiter further adapted to communicate via said bus, it smart retry method comprising the steps of: a.) upon receiving at one of said plurality of slave devices a data transfer request from a master device, said one of said plurality of slave devices generating a first signal; b.) receiving said first signal at a logic system, said logic system adapted to prevent access by said master at each said one of said plurality of slave devices, wherein said logic system is also adapted to prevent access by said master to said bus; c.) said logic system preventing said master device from accessing said one, of said plurality of slave devices until said one of said plurality of slave devices generates a second signal.

2. The smart retry method of claim 1 wherein said second signal of step c.) is generated by de-asserting said first signal.

3. The smart retry method of claim 1 wherein said logic system is adapted to reside on a PCI (peripheral component interconnect) system.

4. The smart retry method of claim 3 wherein said logic system is integral with a target device.

5. The smart retry method of claim 3 wherein said logic system is integral with said arbiter.

6. A PCI arbiter comprising: a normal PCI arbiter logic component adapted to communicate via a PCI bus and to regulate access to said PCI bus by a PCI initiator agent and a plurality of PCI target agents; and a masking logic component coupled to said PCI arbiter, said masking logic component adapted to prevent said PCI initiator agent from accessing said each one of said plurality of PCI target agents when a corresponding said each one of said plurality of PCI target agents generates a denial signal, wherein said logic masking system is adapted to prevent said PCI initiator agent from accessing said PCI bus when said PCI target agent generates said denial signal.