Processor Including a Translation Unit for Selectively Translating Virtual Addresses of Different Sizes Using a Plurality of Paging Tables and Mapping Mechanisms

1. A processor comprising: an execution core configured to generate a virtual address; and a translation unit configured to translate the virtual address to a physical address using: if a first operating mode is selected, either a first page mapping mechanism or a second page mapping mechanism, wherein both the first page mapping mechanism and the second page mapping mechanism are configured to support virtual addresses having at most a first number of bits; and if a second operating mode is selected, a third page mapping mechanism configured to support virtual addresses having more than the first number bits; wherein the translation unit is configured to translate the virtual address to the physical address using the third page mapping mechanism both when a first virtual address size having more than the first number of bits is selected and when a second virtual address size having at most the first number of bits is selected.

2. The processor of claim 1 , wherein the first number of bits is 32.

3. The processor of claim 1 , further comprising a configuration register configured to store an operating mode indication, wherein the translation unit is configured to translate the virtual address to the physical address using either the first page mapping mechanism or the second page mapping mechanism if the operating mode indication indicates a first operating mode, and wherein the translation unit is configured to translate the virtual address to the physical address using the third page mapping mechanism if the operating mode indication indicates a second operating mode.

4. The processor of claim 1 , wherein the first page mapping mechanism supports 2 Megabyte (Mb) pages of physical memory and wherein the second page mapping mechanism supports 4 Mb pages of physical memory.

5. The processor of claim 1 , wherein the third page mapping mechanism comprises at least four levels of paging tables.

6. The processor of claim 1 , wherein the translation unit is implemented in microcode coded to use one of the first page mapping mechanism, the second page mapping mechanism, and the third page mapping mechanism by accessing a plurality of paging tables comprised in each page mapping mechanism in order to obtain the physical address corresponding to the virtual address.

7. The processor of claim 1 , wherein each of the first page mapping mechanism, the second page mapping mechanism, and the third page mapping mechanism comprises a plurality of paging tables, wherein a same page directory base register is used to store a pointer to a first base address of a first paging table in a currently active one of the first, second, and third page mapping mechanisms irrespective of which of the first, second, or third page mapping mechanisms is the currently active one.

8. A processor comprising: an execution core configured to generate a virtual address; and a translation unit configured to translate the virtual address to a physical address using: if a first operating mode is selected, either a first or a second plurality of paging tables, wherein each of the paging tables in the first plurality comprises a plurality of entries that each have a first entry size, wherein each of the paging tables in the second plurality comprises a plurality of entries that each have a second entry size, wherein the second entry size is greater than the first entry size, and wherein the first plurality of paging tables and the second plurality of paging tables are each configured to support virtual addresses having at most a first number of bits; and if a second operating mode is selected, a third plurality of paging tables, wherein each of the paging tables in the third plurality comprises a plurality of entries that have the second entry size, wherein there are more levels of paging tables in the third plurality of paging tables than in the second plurality of paging tables, and wherein the third plurality of paging tables is configured to support virtual addresses having more than the first number of bits; wherein the translation unit is configured to translate the virtual address to the physical address using the third page mapping mechanism both when a first virtual address size having more than the first number of bits is selected and when a second virtual address size having at most the first number of bits is selected.

9. The processor of claim 8 , further comprising a configuration register configured to store an operating mode indication, wherein the translation unit is configured to translate the virtual address to the physical address using either the first plurality of paging tables or the second plurality of paging tables if the operating mode indication indicates a first operating mode, and wherein the translation unit is configured to translate the virtual address to the physical address using the third plurality of paging tables if the operating mode indication indicates a second operating mode.

10. The processor of claim 8 , wherein the second plurality of paging tables and the third plurality of tables each supports 2 Mb pages of physical memory and wherein the first plurality of paging tables supports 4 Mb pages of physical memory.

11. The processor of claim 8 , wherein the third plurality comprises at least four paging tables.

12. The processor of claim 8 , wherein the first number of bits is 32.