High Speed Transmission System with Clock Inclusive Balaced Coding

1. A data transmission system, comprising: at least one encoder that encodes data input and control input values of n-bits into encoded values of m-bits, where m is greater than n, each encoded value having one set of bits when a corresponding clock signal has a first value, and a complementary set of bits when the corresponding clock signal has a second value.

2. The data transmission system of claim 1 , wherein: m is an even number and a DC component of the encoded values when added to the corresponding clock signal is less than two and greater than negative two.

3. The data transmission system of claim 1 , wherein: a DC component of the encoded values is no more than, two and greater than negative one when the corresponding clock signal is low, and greater than negative three and less than one when the corresponding clock signal is high.

4. The data transmission system of claim 2 , wherein: m is ten and n is eight, and selected of the encoded values have a DC component of 0 while other encoded values have a DC component of 2 when the corresponding clock signal is low and 2 when the corresponding clock signal is high.

5. The data transmission system of claim 1 , wherein: m is ten and the encoded values include two portions, each portion having 5 bits and a DC component with an absolute value of less than 2.

6. The data transmission system of claim 1 , wherein: the encoded values and data values are monotonic with respect to one another.

7. The data transmission system of claim 1 , wherein: m is an odd number and DC components of the encoded values are less than two and greater than negative one when the corresponding clock signal is low and greater than negative two and less than one when the corresponding clock signal is high.

8. The data transmission system of claim 1 , wherein: the at least one encoder further receives at least one control indication and generates control values instead of encoded data values when the at least one control indication is active.

9. The data transmission system of claim 8 , wherein: the control values include stress bias codes having an overall DC component that is greater than 2 when the corresponding clock signal is low and less than 2 when the corresponding clock signal is high.

10. The data transmission system of claim 8 , wherein: the control values include a clock skew evaluation sequence in which all the bits of the control value simultaneously transition from one value to a different value.

11. The data transmission system of claim 1 , wherein: the encoder generates an idle value when data input values are not transmitted as encoded values, the idle value having a DC component that is no more than two and greater than negative one when the corresponding clock signal is low and greater than negative three and no more than one when the corresponding clock signal is high.

12. A data transmission system, comprising: a receiver having a plurality of differential receiver circuits each including a value input and a reference input, the differential receiver circuits including a plurality of data receiver circuits having value inputs coupled to data inputs and a clock receiver circuit having a value input coupled to a clock input, the reference input of the data receiver circuit and clock receiver input being commonly coupled to a reference node; and the receiver further includes at least one decoder that decodes encoded values of m-bits into data values of n-bits, where n is less than m, and the encoded values include decode-to-data values and control values, the decode-to-data and control values having one encoded value when a clock signal is high, and a different value when a clock signal is low.

13. The data transmission system of claim 12 , wherein: m is an even number and DC components of the encoded values when added with a corresponding clock signal have an absolute value no greater than one.

14. The data transmission system of claim 13 , wherein: m is ten and n is eight, and selected of the encoded values have a DC component 0 while other encoded values have a DC component of 2 when the corresponding clock signal is low and 2 when the corresponding clock signal is high.

15. The data transmission system of claim 12 , wherein: the encoded values include at least two portions having essentially the same number of bits, an absolute DC component value of each portion being no greater than one.

16. The data transmission system of claim 12 , wherein: m is an odd number and DC components of the encoded values are less than two and greater than negative one when the corresponding clock signal is low and greater than negative two and less than one when the corresponding clock signal is high.

17. The data transmission system of claim 12 , wherein: the at least one decoder includes a plurality of decoders that each receive an encoded data value and generate data values.

18. The data transmission system of claim 17 , further including: a merging circuit for merging a plurality of data values from different decoders to generate an output value.

19. The data transmission system of claim 12 , wherein: the at least one decoder further provides at least one decoded control value in conjunction with a data value and activates the at least one decoded control value when the control value is received and deactivates the at least one decoded control value when an encoded data value is received.

20. The data transmission system of claim 12 , wherein: the control values include stress bias codes having an overall DC component having an absolute value that is greater than 1.

21. The data transmission system of claim 12 , wherein: the at least one decoder includes at least one first look-up table that receives a first table input value and generates at least first portions of data values.

22. The data transmission system of claim 21 , wherein: the at least one decoder further includes at least one second look-up table that receives a second table input value and generates at least second portions of data values, the second table input values including at least second portions of encoded data values.

23. The data transmission system of claim 22 , wherein: the at least one decoder further includes selecting means for generating second portions of data values according to an index values generated from the at least one first look-up table, each index value corresponding to a first portion of a data value.

24. The data transmission system of claim 12 , wherein: the encoded data values and data values are monotonic with respect to one another.

25. The data transmission system of claim 12 , wherein: the reference node is coupled to a filter circuit.

26. The data transmission system of claim 25 , wherein: the filter circuit includes a resistance coupled to the reference node and a capacitor coupled between the reference node and a supply node.

27. A method, comprising the steps of: converting between data and control code values and encoded values that are transmitted in parallel with corresponding half clock cycles, an absolute DC component of each encoded value when summed with the value of the corresponding half clock cycle being no greater than one.

28. The method of claim 27 , wherein: each encoded value includes an even number of bits and DC components of the encoded values corresponding to high half clock cycles are 0 or 2 and the DC components of encoded values corresponding to low half clock cycles are 0 or 2.

29. The method of claim 27 , flier including: each encoded value includes two portions of 5 bits each.

30. The method of claim 27 , wherein: the data values have 8 bits and the corresponding encoded values have 10 bits, and comprises the following data value to encoded value relationships when the corresponding half clock cycle is high: Data Data Data Value Code Value Code Data Value Code Value Code 00000000 00101 00011 00100000 00110 10011 01000000 01001 10101 01100000 01011 10001 00000001 00101 00101 00100001 00110 10100 01000001 01001 10110 01100001 01011 10010 00000010 00101 00110 00100010 00110 10101 01000010 01001 11000 01100010 01011 10100 00000011 00101 00111 00100011 00110 10110 01000011 01001 11001 01100011 01011 11000 00000100 00101 01001 00100100 00110 11000 01000100 01001 11010 01100100 01100 00011 00000101 00101 01010 00100101 00110 11001 01000101 01001 11100 01100101 01100 00101 00000110 00101 01011 00100110 00110 11010 01000110 01010 00011 01100110 01100 00110 00000111 00101 01100 00100111 00110 11100 01000111 01010 00101 01100111 01100 00111 00001000 00101 01101 00101000 00111 00011 01001000 01010 00110 01101000 01100 01001 00001001 00101 01110 00101001 00111 00101 01001001 01010 00111 01101001 01100 01010 00001010 00101 10001 00101010 00111 00110 01001010 01010 01001 01101010 01100 01011 00001011 00101 10010 00101011 00111 01001 01001011 01010 01010 01101011 01100 01100 00001100 00101 10011 00101100 00111 01010 01001100 01010 01011 01101100 01100 01101 00001101 00101 10100 00101101 00111 01100 01001101 01010 01100 01101101 01100 01110 00001110 00101 10101 00101110 00111 10001 01001110 01010 01101 01101110 01100 10001 00001111 00101 10110 00101111 00111 10010 01001111 01010 01110 01101111 01100 10010 00010000 00101 11000 00110000 00111 10100 01010000 01010 10001 01110000 01100 10011 00010001 00101 11001 00110001 00111 11000 01010001 01010 10010 01110001 01100 10100 00010010 00101 11010 00110010 01001 00011 01010010 01010 10011 01110010 01100 10101 00010011 00101 11100 00110011 01001 00101 01010011 01010 10100 01110011 01100 10110 00010100 00110 00011 00110100 01001 00110 01010100 01010 10101 01110100 01100 11000 00010101 00110 00101 00110101 01001 00111 01010101 01010 10110 01110101 01100 11001 00010110 00110 00110 00110110 01001 01001 01010110 01010 11000 01110110 01100 11010 00010111 00110 00111 00110111 01001 01010 01011011 01010 11001 01110111 01100 11100 00011000 00110 01001 00111000 01001 01011 01011000 01010 11010 01111000 01101 00011 00011001 00110 01010 00111001 01001 01100 01011001 01010 11100 01111001 01101 00101 00011010 00110 01011 00111010 01001 01101 01011010 01011 00011 01111010 01101 00110 00011011 00110 01100 00111011 01001 01110 01011011 01011 00101 01111011 01101 01001 00001100 00110 01101 00111100 01001 10001 01001100 01011 00110 01101100 01101 01010 00011101 00110 01110 00111101 01001 10010 01011101 01011 01001 01111101 01101 01100 00011110 00110 10001 00111110 01001 10011 01011110 01011 01010 01111110 01101 10001 00011111 00110 10010 00111111 01001 10100 01011111 01011 01100 01111111 01101 10010 10000000 01101 10100 10100000 10010 00011 11000000 10100 00110 11100000 10110 01010 10000001 01101 11000 10100001 10010 00101 11000001 10100 00111 11100001 10110 01100 10000010 01110 00011 10100010 10010 00110 11000010 10100 01001 11100010 10110 10001 10000011 01110 00101 10100011 10010 00111 11000011 10100 01010 11100011 10110 10010 10000100 01110 00110 10100100 10010 01001 11000100 10100 01011 11100100 10110 10100 10000101 01110 01001 10100101 10010 01010 11000101 10100 01100 11100101 10110 11000 10000110 01110 01010 10100110 10010 01011 11000110 10100 01101 11100110 11000 00011 10000111 01110 01100 10100111 10010 01100 11000111 10100 01110 11100111 11000 00101 10001000 01110 10001 10101000 10010 01101 11001000 10100 10001 11101000 11000 00110 10001001 01110 10010 10101001 10010 01110 11001001 10100 10010 11101001 11000 00111 10001010 01110 10100 10101010 10010 10001 11001010 10100 10011 11101010 11000 01001 10001011 01110 11000 10101011 10010 10010 11001011 10100 10100 11101011 11000 01010 10001100 10001 00011 10101100 10010 10011 11001100 10100 10101 11101100 11000 01011 10001101 10001 00101 10101101 10010 10100 11001101 10100 10110 11101101 11000 01100 10001110 10001 00110 10101110 10010 10101 11001110 10100 11000 11101110 11000 01101 10001111 10001 00111 10101111 10010 10110 11001111 10100 11001 11101111 11000 01110 10010000 10001 01001 10110000 10010 11000 11010000 10100 11010 11110000 11000 10001 10010001 10001 01010 10110001 10010 11001 11010001 10100 11100 11110001 11000 10010 10010010 10001 01011 10110010 10010 11010 11010010 10101 00011 11110010 11000 10011 10010011 10001 01100 10110011 10010 11100 11010011 10101 00101 11110011 11000 10100 10010100 10001 01101 10110100 10011 00011 11010100 10101 00110 11110100 11000 01010 10010101 10001 01110 10110101 10011 00101 11010101 10101 01001 11110101 11000 10110 10010110 10001 10001 10110110 10011 00110 11010110 10101 01010 11110110 11000 11000 10010111 10001 10010 10110111 10011 01001 11010111 10101 01100 11110111 11000 11001 10011000 10001 10011 10111000 10011 01010 11011000 10101 10001 11111000 11000 11010 10011001 10001 10100 10111001 10011 01100 11011001 10101 10010 11111001 11000 11100 10011010 10001 10101 10111010 10011 10001 11011010 10101 10100 11111010 11001 00011 10011011 10001 10110 10111011 10011 10010 11011011 10101 11000 11111011 11001 00101 10001100 10001 11000 10111100 10011 10100 11001100 10110 00011 11101100 11001 00110 10011101 10001 11001 10111101 10011 11000 11011101 10110 00101 11111101 11001 01001 10011110 10001 11010 10111110 10100 00011 11011110 10110 00110 11111110 11001 01010 10011111 10001 11100 10111111 10100 00101 11011111 10110 01001 11111111 11001 01100 and the encoded values have complementary bit values when the corresponding half clock cycle is low.

31. The method of claim 27 , wherein: the data values and corresponding encoded values are monotonic with respect to one another.

32. The method of claim 27 , further including: converting between data values and encoded values when a control indicator has one value, and between control code values and encoded values when the control indicator has another value, the control code values being different than the data values.

33. The method of claim 32 , wherein: the encoded values include stress codes, an absolute DC component of each stress code when summed with the value of the corresponding half clock cycle being greater than one.

34. The method of claim 27 , wherein: converting between data values and encoded values includes decoding encoded values into data values, the decoding data values includes storing first portions of data values; and accessing first portions of data values with first portions of the encoded values.

35. The method of claim 34 , wherein: decoding data values further includes storing second portions of data values; accessing stored second portions of data values with at least second portions of the encoded values.

36. The method of claim 35 , wherein: decoding data values further includes storing type values corresponding to first portions of the encoded values; accessing stored type values with the first portions of the encoded values; accessing stored second portions of data values with the second portions of the encoded values and the type values.