Data Consistency Memory Management System and Method and Associated Multiprocessor Network

1. System for memory management of data consistency relating to a main memory accessible by at least two processors, at least one of the said processors being furnished with at least one cache memory associated with at least one area of the main memory, referred to as the assignment area of said processor, the said management system comprising: an assembly for management of shared access of said processors to at least one common area of the main memory, referred to as the exchanges area, at least one copy module respectively associated with at least a first of said processors furnished with at least one cache memory, capable of performing a data copy between a memory workspace consisting of one of said cache memories and/or the assignment area of said first processor, on the one hand, and the exchanges area, on the other hand, and at least one data transfer module, associated respectively with at least one second processor capable of exchanging data with said first processor, intended for transferring data between said exchanges area and said associated second processor, characterized in that said consistency management system also comprises triggering means controlled by said second processor, capable of triggering the copy modules of the first processor and the transfer modules of said second processors when said first processor submits requests involving transfers of data between said memory workspaces of the first processor and said second processor.

2. Memory management system according to claim 1 , characterized in that said second processor are fitted with memory space allocation modules, capable of allocating common spaces in said exchanges area, said triggering means being capable of triggering said memory space allocation modules when the said first processor submits requests involving transfers of data between said memory workspaces of the said first processor and the said second processor, by bringing about the allocation of the common spaces necessary for the said data.

3. Memory management system according to claim 1 , characterized in that said triggering means comprise at least one interrupt device between said first processor and second processor capable of exchanging data, said device being intended to signal an exchange of data between said processor and to bring about a temporary interruption of processing operations in progress in said processor.

4. Memory management system according to claim 3 , characterized in that said interrupt devices comprise hardware mechanisms.

5. Memory management system according to claim 1 , characterized in that the copy module of said first processor is designed to perform a data copy from the said exchanges area to said memory workspace of said first processor and in that the said transfer modules of the second processor is capable of exchanging data with said first processor are designed to transfer data from the said second processor to said exchanges area.

6. Memory management system according to claim 1 , characterized in that the copy module of said first processor is designed to perform a data copy from said memory workspace of said first processor to said exchanges area and in that said transfer modules of said second processor capable of exchanging data with said first processor are designed to transfer data from said exchanges area to said second processor.

7. Memory management system according to claim 1 , characterized in that the assignment areas of the processor with cache memories are positioned outside said exchanges area, and the assembly for management of shared access to the exchanges area is designed for a non-hidden area.

8. Memory management system according to claim 1 , characterized in that at least one of the assignment areas of the processor with cache memories contains said exchanges area, and the assembly for management of shared access to the exchanges area comprises a hardware device capable of ensuring the consistency of said exchange area.

9. Multiprocessor network comprising a main memory and at least two processors, at least one of said processor being furnished with a cache memory associated with at least one area of the main memory, referred to as the assignment area of the said processor, characterized in that said multiprocessor network comprises a system for memory management of data consistency relating to a main memory accessible by at least two processors, at least one of the said processors being furnished with at least one cache memory associated with at least one area of the main memory, referred to as the assignment area of said processor, the said management system comprising: an assembly for management of shared access of said processors to at least one common area of the main memory, referred to as the exchanges area, at least one copy module respectively associated with at least a first of said processors furnished with at least one cache memory, capable of performing a data copy between a memory workspace consisting of one of said cache memories and/or the assignment area of said first processor, on the one hand, and the exchanges area, on the other hand, and at least one data transfer module, associated respectively with at least one second processor capable of exchanging data with said first processor, intended for transferring data between said exchanges area and said associated second processor, characterized in that said consistency management system also comprises triggering means controlled by said second processor, capable of triggering the copy modules of the first processor and the transfer modules of said second processors when said first processor submits requests involving transfers of data between said memory workspaces of the first processor and said second processor.

10. Method for memory management of data consistency relating to a main memory accessible by at least two processor, at least one of said processor being furnished with at least one cache memory associated with at least one area of the main memory, referred to as the assignment area of said processor, in which the shared access of said processor to at least one common area of the main memory, referred to as the exchanges area, is managed in such a way that during a transfer of data from at least a first of the said processor furnished with at least one cache memory to a second of said processor, a copying of said data from a memory workspace consisting of one of said cache memories and/or the assignment area of the first processor, to the exchanges area is triggered, and a transfer of said data from the exchanges area to said second processor is triggered, and/or during a transfer of data from said second processor to said first processor; a transfer of said data from the said second processor to the exchanges area is triggered, and a copying of said data from the exchanges area to the memory workspace of the first processor is triggered, characterized in that when a request involving a transfer of data from the memory workspace of the first processor to the second processor is sent by means of the first processor and/or when a request involving a transfer of data from the second processor to the memory workspace of the first processor is sent by means of the first processor, said copying and said transfer of the data are triggered by means of the second processor.