Leading Bit Prediction with In-Parallel Correction

1. A method, comprising: performing a mathematical operation involving two floating point numbers to produce a result; predicting an amount of shift needed to normalize the result using the two floating point numbers; and identifying a correction to the predicted shift amount using only the two floating point numbers.

2. The method of claim 1 , further comprising shifting the result based on at least one of the predicted shift amount and the correction to produce a normalized result.

3. The method of claim 2 , wherein shifting the result comprises shifting at least one of a fraction portion of the result and an exponent portion of the result.

4. The method of claim 1 , wherein identifying the correction comprises: detecting one of a M 0 sequence and a P 0 sequence in a bitwise combination of fraction portions of the two floating point numbers; determining whether a 0 M sequence follows the detected M 0 or P 0 sequence; and determining that a correction is needed to the predicted shift amount when a 0 M sequence follows the detected M 0 or P 0 sequence.

5. The method of claim 1 , wherein identifying the correction comprises: detecting a second occurrence of a 0 P or 0 M sequence in a bitwise combination of fraction portions of the two floating point numbers; determining whether the second occurrence is a 0 M sequence; and determining that a correction is needed to the predicted shift amount when the second occurrence is a 0 M sequence.

6. The method of claim 5 , wherein identifying the correction further comprises generating signals identifying a quantity and a location of at least one of the 0 P and 0 M sequences in the bitwise combination.

7. The method of claim 1 , wherein the performing, predicting, and identifying steps are initiated concurrently or simultaneously.

8. A system, comprising: a memory operable to store two floating point numbers; and a processor operable to: perform a mathematical operation involving the two floating point numbers to produce a result; predict an amount of shift needed to normalize the result using the two floating point numbers; and identify a correction to the predicted shift amount using only the two floating point numbers.

9. The system of claim 8 , wherein the processor is further operable to shift the result based on at least one of the predicted shift amount and the correction to produce a normalized result.

10. The system of claim 8 , wherein the processor is operable to identify the correction by: detecting a second occurrence of a 0 P or 0 M sequence in a bitwise combination of fraction portions of the two floating point numbers; determining whether the second occurrence is a 0 M sequence; and determining that a correction is needed to the predicted shift amount when the second occurrence is a 0 M sequence.

11. The system of claim 10 , wherein the processor is further operable to identify the correction by generating signals identifying a quantity and a location of at least one of the 0 P and 0 M sequences in the bitwise combination.

12. The system of claim 8 , wherein the processor is operable to perform the performing, predicting, and identifying functions concurrently or simultaneously.

13. Logic circuitry, comprising: an adder operable to perform a mathematical operation involving two floating point numbers to produce a result; a leading bit predictor operable to predict an amount of shift needed to normalize the result using the two floating point numbers; and a predictor corrector operable to identify a correction to the predicted shift amount using only the two floating point numbers.

14. The logic circuitry of claim 13 , further comprising a shifter operable to shift the result based on at least one of the predicted shift amount and the correction to produce a normalized result.

15. The logic circuitry of claim 13 , wherein the predictor corrector is operable to identify the correction by: detecting a second occurrence of a 0 P or 0 M sequence in a bitwise combination of fraction portions of the two floating point numbers; determining whether the second occurrence is a 0 M sequence; and determining that a correction is needed to the predicted shift amount when the second occurrence is a 0 M sequence.

16. The logic circuitry of claim 13 , wherein the predictor corrector comprises a plurality of pattern analysis logic blocks, each of the pattern analysis logic blocks operable to generate signals identifying a quantity and a location of at least one of the 0 P and 0 M sequences in the bitwise combination.

17. The logic circuitry of claim 13 , wherein the adder, the leading bit predictor, and the predictor corrector receive the two floating point numbers concurrently or simultaneously.

18. A system, comprising: means for performing a mathematical operation involving two floating point numbers to produce a result; means for predicting an amount of shift needed to normalize the result using the two floating point numbers; and means for identifying a correction to the predicted shift amount using only the two floating point numbers.

19. A method comprising: storing integer and floating point instructions in a system memory; fetching the instructions from the system memory; and executing the instructions in a processor, the processor operable during execution of the instructions to: perform a mathematical operation involving two floating point numbers to produce a result; predict an amount of shift needed to normalize the result using the two floating point numbers; and identify a correction to the predicted shift amount using only the two floating point numbers.

20. A processor, comprising: a floating point unit; the floating point unit comprising an add unit; the add unit operable to: perform a mathematical operation involving two floating point numbers to produce a result; predict an amount of shift needed to normalize the result using the two floating point numbers; and identify a correction to the predicted shift amount using only the two floating point numbers.

21. A method, comprising: receiving two floating point numbers; and using only the two floating point numbers to identify a correction to a predicted shift amount, the predicted shift amount representing a predicted amount that a sum or difference of the two floating point numbers needs to be shifted to normalize the result.

22. A predictor corrector, comprising: a plurality of pattern analysis logic blocks; the pattern analysis logic blocks collectively operable to: receive two floating point numbers; and use only the two floating point numbers to identify a correction to a predicted shift amount, the predicted shift amount representing a predicted amount that a sum or difference of the two floating point numbers needs to be shifted to normalize the result.

23. The predictor corrector of claim 22 , wherein the logic blocks are collectively operable to generate signals identifying a quantity and a location of at least one of 0 P and 0 M sequences in a bitwise combination of fraction portions of the two floating point numbers.

24. Logic circuitry comprising a predictor corrector, the predictor corrector operable to: receive two floating point numbers; and use only the two floating point numbers to identify a correction to a predicted shift amount, the predicted shift amount representing a predicted amount that a sum or difference of the two floating point numbers needs to be shifted to normalize the result.