Method for Converting a Logic Circuit Model

1. A method for converting an RT (Register Transfer)-level model of a logic circuit block into a high abstraction-level operation model, comprising the steps of: setting one or more states of the logic circuit block as operation start states and operation end states by using input/output instruction information that represents a relation between an input/output instruction of the logic circuit block and an input/output signal corresponding to the input/output instruction; and analyzing operation of the logic circuit block, the operation analyzing step being conducted by selecting one input instruction to be analyzed from those included in the input/output instruction information, applying an input signal corresponding to the selected input instruction to the RT-level model that is in a first state selected from the operation start states, and analyzing the RT-level model and extracting an operation of the logic circuit block by varying the input signal, until the RT-level model reaches a second state of the operation end states, wherein the operation analyzing step is repeatedly conducted for at least one or all combinations of the operation start state and the input instruction included in the input/output instruction information, and the operation model of the logic circuit block is produced based on the extracted operations.

2. The method according to claim 1 , wherein the operation analyzing step includes the steps of producing a time series of one or more input signals corresponding to the instruction to be analyzed, producing a time series of an output signal by executing the RT-level model using the time series of the input signals until the RT-level model reaches the second state, extracting a state where the RT-level model reaches the second state as an operation of the logic circuit block, and comparing the time series of the output signal with the relation between an output instruction and an output signal corresponding thereto as defined in the input/output instruction information, and extracting the output instruction from those included in the input/output instruction information as an operation of the logic circuit block.

3. The method according to claim 1 , wherein the operation analyzing step includes the steps of producing at every clock one or more input signals corresponding to an input instruction included in the instruction to be analyzed, executing the RT-level model at every clock using the input signals, and producing an output signal at every clock, extracting at every clock a state where the RT-level model reaches the second state as an operation of the logic circuit block, and comparing the output signal with the relation between an output instruction and an output signal corresponding thereto as defined in the input/output instruction infromation, and extracting at every clock the output instruction from those included in the input/output instruction information as an operation of the logic circuit block.

4. The method according to claim 3 , wherein the input/output instruction information includes as an output instruction an output instruction with a response signal, the output instruction with the response signal being an instruction having both an output signal and an input signal associated therewith as a response signal thereof, and in the operation analyzing step, when the output instruction with the response signal is extracted at one clock, operation of the RT-level model at a clock later than the one clock is analyzed by using the response signal produced by varying a value of the response signal corresponding to the output instruction with the response signal at a timing designated by the input/output instruction information.

5. The method according to claim 3 , wherein the input/output instruction information includes as an input instruction an input instruction with a response signal, the input instruction with the response signal being an instruction having both an input signal and an output signal associated therewith as a response signal thereof, and in the operation analyzing step, when the input instruction with the response signal is selected at one clock as the instruction to be analyzed, operation of the RT-level model at a clock later than the one clock is analyzed by using the response signal produced based on a value of the response signal corresponding to the input instruction with the response signal, which varies at a timing designated by the input/output instruction information.

6. The method according to claim 3 , wherein the input/output instruction information includes as an output instruction an output instruction with a return value, the output instruction with the return value being an instruction having an input signal associated therewith as a return value, and in the operation analyzing step, when operation of the RT-level model varies according to a value of the input signal serving as the return value of the output instruction, operation of the RT-level model is analyzed for every possible combination of values of the return value.

7. The method according to claim 3 , wherein the input/output instruction information includes as an input instruction an input instruction with a return value, the input instruction with the return value being an instruction having an output signal associated therewith as a return value, and in the operation analyzing step, a value of the output signal at a clock designated by the input/output instruction information is extracted as the return value of the input instruction, and operation of the RT-level model is analyzed based on the extracted value.

8. The method according to claim 1 , wherein, in the state setting step, a state where a state of the logic circuit block does not change in the absence of an input instruction or a state where a finite number of states of the logic circuit block are repeated in the absence of an input instruction are set as the operation start states and the operation end states.

9. The method according to claim 1 , wherein, of state variables specifying a state of the logic circuit block, any state variable that affects an output signal used to recognize an output instruction included in the input/output instruction information is selected as a control variable, and one or more states specified by the selected control variable are set as the operation start states and the operation end states in the state setting step.

10. The method according to claim 9 , wherein, of the one or more states designated by the control variable, states where all or at least one of the control variables have the same value are regarded as a single state when the operation start states and the operation end states are set in the state setting step.

11. The method according to claim 9 , wherein, in the state setting step, any state variable that contributes to updating of the control variable in one-clock operation of the RT-level model is also selected as the control variable.