Construction of a Technology Library for Use in an Electronic Design Automation System That Converts the Technology Library into Non-Linear, Gain-Based Models for Estimating Circuit Delay

1. A library construction process comprising the steps of: a) constructing logic functions of a technology library corresponding to a basic cell set wherein each logic function of said basic cell set comprises at least a first predetermined number of discrete cells; b) constructing logic functions of said technology library corresponding to an extended cell set wherein each logic function of said extended cell set comprises at least a second predetermined number of discrete cells; c) determining input pin capacitances of discrete cells of a same logic function such that variances of input pin capacitance ratios do not exceed a percentage threshold and repeating step c) for each logic function of said basic and extended cell sets of said technology library; d) for discrete cells of a same logic function, geometrically distributing sizes of each discrete cell and repeating step d) for each logic function of said basic and extended cell sets of said technology library; and e) saving said technology library in a computer memory.

2. A process as described in claim 1 wherein said first predetermined number of discrete cells is six.

3. A process as described in claim 1 wherein said second predetermined number of discrete cells is five.

4. A process as described in claim 2 wherein said second predetermined number of discrete cells is five.

5. A process as described in claim 1 wherein said percentage threshold is ten percent.

6. A process as described in claim 2 wherein said percentage threshold is ten percent.

7. A process as described in claim 4 wherein said percentage threshold is ten percent.

8. A process as described in claim 1 wherein said basic cell set comprises: inverter gates; NAND gates; and NOR gates.

9. A process as described in claim 1 wherein said extended cell set comprises: AND gates; OR gates; XOR gates; XNOR gates; and multiplexer gates.

10. A process as described in claim 1 further comprising the step of converting said technology library into a scalable cell library wherein said scalable cell library comprises a data structure model for each scalable cell, said data structure model stored in computer readable memory and comprising: a look-up table storing values referenced by gain and input slew, said look-up table providing an output slew value and an output delay value for a given pair of input values comprising: a gain value; and an input slew value, wherein said look-up table is used by computer implemented electronic design automation processes for providing an estimate of a signal delay through an integrated circuit cell, said estimate of said signal delay being used in designing an integrated circuit device and wherein said look-up table models signal delay using a nonlinear function.

11. A computer system comprising a processor coupled to a bus and a memory unit coupled to said bus and having stored thereon instructions that when executed implement a library construction process comprising the steps of: a) constructing logic functions of a technology library corresponding to a basic cell set wherein each logic function of said basic cell set comprises at least a first predetermined number of discrete cells; b) constructing logic functions of said technology library corresponding to an extended cell set wherein each logic function of said extended cell set comprises at least a second predetermined number of discrete cells; c) determining input pin capacitances of discrete cells of a same logic 5 function such that variances of input pin capacitance ratios do not exceed a percentage threshold and repeating step c) for each logic function of said basic and extended cell sets of said technology library; d) for discrete cells of a same logic function, geometrically distributing sizes of each discrete cell and repeating step d) for each logic function of said basic and extended cell sets of said technology library; and e) saving said technology library in a computer memory.

12. A computer system as described in claim 11 wherein said first predetermined number of discrete cells is six.

13. A computer system as described in claim 11 wherein said second predetermined number of discrete cells is five.

14. A computer system as described in claim 12 wherein said second predetermined number of discrete cells is five.

15. A computer system as described in claim 11 wherein said percentage threshold is ten percent.

16. A computer system as described in claim 2 wherein said percentage threshold is ten percent.

17. A computer system as described in claim 14 wherein said percentage threshold is ten percent.

18. A computer system as described in claim 11 wherein said basic cell set comprises: inverter gates; NAND gates; and NOR gates.

19. A computer system as described in claim 11 wherein said extended cell set comprises: AND gates; OR gates; XOR gates; XNOR gates; and multiplexer gates.

20. A computer system as described in claim 11 wherein said process further comprising the step of converting said technology library into a scalable cell library wherein said scalable cell library comprises a data structure model for each scalable cell, said data structure model stored in computer readable memory and comprising: a look-up table storing values referenced by gain and input slew, said look-up table providing an output slew value and an output delay value for a given pair of input values comprising: a gain value; and an input slew value, wherein said look-up table is used by computer implemented electronic design automation processes for providing an estimate of a signal delay through an integrated circuit cell, estimate of said signal delay being used in designing an integrated circuit device and wherein said look-up table models signal delay using a nonlinear function.