Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic apparatus comprising: a microprocessor; a first memory associated with the microprocessor; a second memory; and stored instructions to: block transfer instructions from the second memory to the first memory; rearrange a series of N bytes in the transferred instructions from a second memory space orientation to a first memory space orientation orthogonal to the second memory space orientation thereby forming rearranged bytes; and use the rearranged bytes to initialize the microprocessor.
2. The electronic apparatus of claim 1 wherein the block transfer comprises transferring the instructions to the first memory by direct memory access.
3. The electronic apparatus of claim 1 wherein the second memory is non-volatile memory.
4. The electronic apparatus of claim 3 wherein the second memory is a selective one of read only memory, non-volatile random access memory and an electronically programmable read only memory.
5. The electronic apparatus of claim 1 wherein the first memory is a selective one of a synchronous dynamic random access memory and a cache.
6. The electronic apparatus of claim 1 wherein the transferred instructions are rearranged by horizontally shifting the instructions within the first memory and vertically shifting the instructions within the first memory.
7. A method comprising: providing an electronic apparatus comprising a microprocessor, a first memory associated with the microprocessor and a second memory; and providing instructions to perform acts comprising: block transferring instructions from the second memory to the first memory; rearranging a series of N bytes in the transferred instructions from a second memory space orientation to a first memory space orientation orthogonal to the second memory space orientation thereby forming rearranged bytes; and using the rearranged bytes to initialize the apparatus.
8. The method of claim 7 wherein block transferring comprises transferring the instructions to the first memory by direct memory access.
9. The method of claim 7 wherein the second memory is non-volatile memory.
10. The method of claim 9 wherein the second memory is a selective one of read only memory, non-volatile random access memory and an electronically programmable read only memory.
11. The method of claim 7 wherein the first memory is a selective one of a synchronous dynamic random access memory and a cache.
12. The method of claim 7 wherein rearranging comprises horizontally shifting the instructions within the first memory and vertically shifting the instructions within the first memory.
13. A method comprising: block transferring instructions from a second memory to a first memory associated with a microprocessor-based controller; rearranging a series of N bytes in the transferred instructions from a second memory space orientation to a first memory space orientation orthogonal to the second memory space orientation, thereby forming rearranged bytes; and using the rearranged bytes to initialize the microprocessor-based controller.
14. The method of claim 13 further comprising using the initialized microprocessor-based controller to process data received from a media source for output via a media output device.
15. The method of claim 13 wherein block transferring comprises transferring the instructions to the first memory by direct memory access.
16. The method of claim 13 wherein the second memory is non-volatile memory.
17. The method of claim 16 wherein the second memory is a selective one of read only memory, non-volatile random access memory and an electronically programmable read only memory.
18. The method of claim 13 wherein the first memory is a selective one of a synchronous dynamic random access memory and a cache.
19. The method of claim 13 wherein rearranging comprises horizontally shifting the instructions within the first memory and vertically shifting the instructions within the first memory.
20. A computer-readable medium comprising instructions to: block transfer instructions from a second memory to a first memory associated with a microprocessor; rearrange a series of N bytes in the transferred instructions from a second memory space orientation to a first memory space orientation orthogonal to the second memory space orientation thereby forming rearranged bytes; and use the rearranged bytes to initialize a microprocessor.
21. The computer-readable medium of claim 20 wherein the block transfer comprises transferring the instructions to the first memory by direct memory access.
22. The computer-readable medium of claim 20 wherein the second memory is non-volatile memory.
23. The computer-readable medium of claim 22 wherein the second memory is a selective one of read only memory, non-volatile random access memory and an electronically programmable read only memory.
24. The computer-readable medium of claim 20 wherein the first memory is a selective one of a synchronous dynamic random access memory and a cache.
25. The computer-readable medium of claim 20 wherein the transferred instructions are rearranged by horizontally shifting the instructions within the first memory and vertically shifting the instructions within the first memory.
Unknown
October 19, 2004
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