Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of minimizing time for performing optical proximity correction (OPC) on a chip layout, the method comprising: identifying a set of repeating structures within defined design units, each instance of the repeating structures having substantially the same proximity effect environment within a predetermined distance; pre-processing a representative repeating structure in the set of repeating structures during a non-critical time in chip design; and based on the pre-processing, performing the OPC on the chip layout.
2. The method of claim 1 , wherein identifying includes accessing a library of standard cells.
3. The method of claim 1 , wherein identifying includes receiving layout data.
4. The method of claim 1 , wherein a defined design unit includes at least one of: a standard cell, an inner core of a standard cell, a memory cell, an input/output pad, an IP core, a data path, and a custom block.
5. The method of claim 1 , wherein pre-processing is performed only on static structures.
6. The method of claim 1 , wherein the non-critical time is after identifying but before OPC.
7. The method of claim 1 , further including instantiating structures in the set of repeating structures before OPC.
8. The method of claim 1 , wherein results of the pre-processing include at least one of dissection and evaluation points for segments, contrast images at the evaluation points, and corrected versions of the repeating structures.
9. The method of claim 1 , wherein the predetermined distance is a function of the proximity effect range.
10. A method of designing a library of standard cells, the method comprising: identifying repeating structures in at least one of the standard cells, wherein a set of repeating structures has substantially the same proximity effect environment within a predetermined range; pre-processing one of the set of repeating structures for optical proximity correction during a non-critical time in chip design; and storing results of the pre-processing.
11. The method of claim 10 , wherein identifying can be done during creation of the standard cells, wherein the standard cells are optimized to maximize the occurrence of repeating structures.
12. The method of claim 10 , wherein repeating structures can include at least one of segments, shapes, polygons, and groups of polygons.
13. The method of claim 10 , wherein repeating structures can be grouped in the cores of the standard cells and other structures less static than the repeating structures can be placed in the perimeters of the standard cells.
14. The method of claim 10 , wherein the results of the pre-processing include at least one of dissection and evaluation points for segments, contrast images at the evaluation points, and corrected versions of the repeating structures.
15. The method of claim 10 , wherein storing the results can be done within a standard cell layout.
16. The method of claim 15 , wherein the standard cell layout includes hierarchical data and the results are stored on a layer of the hierarchical data.
17. The method of claim 15 , wherein the standard cell layout includes hierarchical data and the results are stored on a layer of the hierarchical data dedicated to the results.
18. The method of claim 10 , wherein storing the results can include a separate data file associated with the library.
19. The method of claim 10 , wherein the standard cells and the results of the pre-processing are provided in GDS-II format.
20. A storage means accessible by an optical proximity correction (OPC) tool, the storage means including: pre-processed structures associated with a plurality of design units, wherein the pre-processed structures were created during a non-critical time in chip design, wherein each set of pre-processed structures has at least substantially the same proximity effect environment within a predetermined distance, and wherein the pre-processed structures can be used to perform OPC on a chip layout.
21. The storage means of claim 20 provided within at least one standard cell layout.
22. The storage means of claim 21 , wherein the standard cell layout includes hierarchical data and the pre-processed structures are stored on one of a first layer with cell data and a second layer dedicated to the pre-processed structures.
23. The storage means of claim 20 provided in a separate data file associated with a standard cell library.
24. The storage means of claim 20 provided within layout data.
25. The storage means of claim 24 , wherein the layout data includes hierarchical data and the pre-processed structures are stored on one of a first layer with a portion of the hierarchical data and a second layer dedicated to the pre-processed structures.
26. A method of minimizing time for performing a processing operation on a chip layout, the method comprising: identifying a set of repeating structures within defined design units, each instance of the repeating structures having substantially the same proximity effect environment within a predetermined distance; pre-processing a representative repeating structure in the set of repeating structures during a non-critical time in chip design; and based on the pre-processing, performing the processing operation on the chip layout.
Unknown
October 19, 2004
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