System & Method for Performing Design Rule Check

1. A method of performing a design rule check on a layout for an integrated circuit (IC) comprising the steps of: (a) providing at least a first set of design rules for a first region of the layout; (b) providing at least a second set of design rules for a second region of the layout; wherein said first region and said second region correspond to different types of circuitry to be embodied in the IC; (c) processing a layer of the layout such that any said first region is checked in accordance with at least said first set of design rules, and said second region is checked in accordance with at least said second set of design rules; (d) generating said second set of design rules by modifying said first set of design rules in accordance with differences in sizings, spacings and/or tolerances manufacturable between said first region and said second region.

2. The method of claim 1 , further including a step (d): generating a report of any errors detected in said first region and/or said second region.

3. The method of claim 1 , wherein said first region is also checked in accordance with said second design rule.

4. The method of claim 1 , wherein said first region includes logic circuitry, and said second region includes one or more types of memory circuitry.

5. The method of claim 1 , further including a step: providing a third set of design rules for a third region used in the IC layout, which third region corresponds to a non-volatile memory.

6. The method of claim 1 , wherein step (c) is performed within a computing system operating on a GDS formatted database tape containing the IC layout.

7. The method of claim 1 , wherein a third region between said first region and said second region is also processed in accordance with said first set of design rules.

8. The method of claim 1 , wherein said second region is identified in said layer through an identifier describing a type of memory implemented in said second region.

9. A method of performing a design rule check on a layout for an integrated circuit (IC) comprising the steps of: (a) providing at least a first set of design rules for a first region of the layout; (b) providing at least a second set of design rules for a second region of the layout; wherein said first region and said second region correspond to different types of circuitry to be embodied in the IC; (c) processing a layer of the layout such that any said first region is checked in accordance with at least said first set of design rules, and said second region is checked in accordance with at least said second set of design rules; (d) generating said second set of design rules by modifying said first set of design rules in accordance with differences in sizings, spacings and/or tolerances manufacturable between said first region and said second region; wherein said second set of design rules are derived by using said first set of design rules to check features of a memory based circuit so that any non-complying features can be identified, said non-complying features being features that do not comply with said first set of design rules.

10. A method of performing a design rule check on a layout for an integrated circuit (IC) comprising the steps of: (a) providing at least a first set of design rules for a first region of the layout; (b) providing at least a second set of design rules for a second region of the layout; wherein said first region and said second region correspond to different types of circuitry to be embodied in the IC; (c) processing a layer of the layout such that any said first region is checked in accordance with at least said first set of design rules, and said second region is checked in accordance with at least said second set of design rules; (d) generating said second set of design rules by modifying said first set of design rules in accordance with differences in sizings, spacings and/or tolerances manufacturable between said first region and said second region; wherein said second set of design rules are derived by using said first set of design rules to check features of a memory based circuit so that any non-complying features can be identified, said non-complying features being features that do not comply with said first set of design rules; (e) identifying a memory based design parameter value associated with the non-complying feature, and using said memory based design parameter value to alter a logic based design parameter value associated with the first set of design rules, so that said memory based design parameter value is used to create said second set of design rules.

11. A method of verifying manufacturability of a system-on-chip (SOC) integrated circuit (IC) which includes a logic circuit portion situated in a first logic region and a memory circuit portion situated in a second memory region, the method comprising the steps of: (a) providing at least a first set of design rules for the first logic region, said first set of design rules specifying first minimum geometric constraints allowable for features in the first logic region; and (b) providing at least a second set of design rules for the second memory region, said second set of design rules specifying second minimum geometric constraints allowable for features in the second memory region; wherein at least some of said first minimum geometric constraints and said second minimum geometric constraints are different; and (c) identifying a first polygon present in a first layer of the SOC, including whether said first polygon corresponds to circuitry for a first logic region and/or a second memory region; and (d) when said first polygon corresponds to a first logic region, checking said first polygon for layout errors in accordance with at least said first set of design rules; and (e) when said first polygon corresponds to a second memory region, checking said second memory region for layout errors in accordance with at least said second set of design rules; and (f) generating an output indicative of any errors detected in a physical layout of the SOC, including in the first logic region and the second memory region; wherein all of steps (a) through (f) are performed by one or more program routines executing on a computing system.

12. The method of claim 11 , wherein said first minimum geometric constraints and said second minimum geometric constraints include one or more of the following: (a) minimum spacings between signal lines; and/or (b) minimum line widths; and/or (c) minimum gate widths.

13. The method of claim 11 , wherein said first layer includes at least two different types of circuitry, including at least one for said first logic region, and at least one for said second memory region.

14. A method of verifying manufacturability of a system-on-chip (SOC) integrated circuit (IC) which includes a logic circuit portion situated in a first logic region and a memory circuit portion situated in a second memory region, the method comprising the steps of: (a) providing at least a first set of design rules for the first logic region, said first set of design rules specifying first minimum geometric constraints allowable for features in the first logic region; and (b) providing at least a second set of design rules for the second memory region, said second set of design rules specifying second minimum geometric constraints allowable for features in the second memory region; (c) providing at least a third set of design rules for an intermediate region located between said first logic region and said second memory region wherein at least some of said first minimum geometric constraints and said second minimum geometric constraints are different; and (d) identifying a first polygon present in a first layer of the SOC, including whether said first polygon corresponds to circuitry for a first logic region and/or a second memory region; and (e) when said first polygon corresponds to a first logic region, checking said first polygon for layout errors in accordance with at least said first set of design rules; and (f) when said first polygon corresponds to a second memory region, checking said second memory region for layout errors in accordance with at least said second set of design rules; and (g) generating an output indicative of any errors detected in a physical layout of the SOC, including in the first logic region and the second memory region; wherein all of steps (a) through (g) are performed by one or more program routines executing on a computing system.

15. A method of verifying manufacturability of a system-on-chip (SOC) integrated circuit (IC) which includes a logic circuit portion situated in a first logic region and a memory circuit portion situated in a second memory region, the method comprising the steps of: (a) providing at least a first set of design rules for the first logic region, said first set of design rules specifying first minimum geometric constraints allowable for features in the first logic region; and (b) providing at least a second set of design rules for the second memory region, said second set of design rules specifying second minimum geometric constraints allowable for features in the second memory region; (c) providing at least a third set of design rules for a third memory region, said third memory region containing a memory circuit with different characteristics than a memory circuit in said second memory region; wherein at least some of said first minimum geometric constraints and said second minimum geometric constraints are different; and (d) identifying a first polygon present in a first layer of the SOC, including whether said first polygon corresponds to circuitry for a first logic region and/or a second memory region; and (e) when said first polygon corresponds to a first logic region, checking said first polygon for layout errors in accordance with at least said first set of design rules; and (f) when said first polygon corresponds to a second memory region, checking said second memory region for layout errors in accordance with at least said second set of design rules; and (g) generating an output indicative of any errors detected in a physical layout of the SOC, including in the first logic region and the second memory region; wherein all of steps (a) through (g) are performed by one or more program routines executing on a computing system.

16. A method of verifying manufacturability of a system-on-chip (SOC) integrated circuit (IC) which includes a logic circuit portion situated in a first logic region and a memory circuit portion situated in a second memory region, the method comprising the steps of: (a) providing at least a first set of design rules for the first logic region, said first set of design rules specifying first minimum geometric constraints allowable for features in the first logic region; and (b) providing at least a second set of design rules for the second memory region, said second set of design rules specifying second minimum geometric constraints allowable for features in the second memory region; (c) providing at least a third set of design rules for a third memory region, said third memory region containing a memory circuit with different characteristics than a memory circuit in said second memory region; wherein said third memory region is a read-only-memory (ROM), and said second memory region is an Static Random Access Memory (SRAM); wherein at least some of said first minimum geometric constraints and said second minimum geometric constraints are different; and (d) identifying a first polygon present in a first layer of the SOC, including whether said first polygon corresponds to circuitry for a first logic region and/or a second memory region; and (e) when said first polygon corresponds to a first logic region, checking said first polygon for layout errors in accordance with at least said first set of design rules; and (f) when said first polygon corresponds to a second memory region, checking said second memory region for layout errors in accordance with at least said second set of design rules; and (g) generating an output indicative of any errors detected in a physical layout of the SOC, including in the first logic region and the second memory region; wherein all of steps (a) through (g) are performed by one or more program routines executing on a computing system.

17. A method of generating design rules for a plurality of different circuit regions to be used on a system-on-chip (SOC) integrated circuit (IC), the method comprising the steps of: (a) providing at least a first set of design rules for a first type of circuit region, said first set of design rules specifying first minimum geometric constraints allowable for features in the first type of circuit region; and (b) generating a second set of design rules for a second type of circuit region based on said first set of design rules, said second set of design rules specifying second minimum geometric constraints allowable for features in the second memory region; wherein step (b) includes the following steps: (b1) checking geometric features of said second type of circuit region against said first set of design rules; and (b2) identifying any errors triggered by said geometric features of said second type of circuit region, said errors corresponding to instances where said geometric figures do not comply with said first set of design rules; and (b3) modifying at least some of said first minimum geometric constraints in said first set of design rules in response to any errors identified in step (b2); wherein said second set of design rules is derived from some of said first minimum geometric constraints and others of said first minimum geometric constraints that have been modified to accommodate characteristics of said geometric features as they may be found in said second type of circuit region; wherein at least some of said first minimum geometric constraints and said second minimum geometric constraints are different; and further wherein said first set of design rules and said second set of design rules are in a form suitable for use by a design rule checking software application.

18. A method of generating design rules for a plurality of different circuit regions to be used on a system-on-chip (SOC) integrated circuit (IC), the method comprising the steps of: (a) providing at least a first set of design rules for a first type of circuit region, said first set of design rules specifying first minimum geometric constraints allowable for features in the first type of circuit region; and (b) generating a second set of design rules for a second type of circuit region based on said first set of design rules, said second set of design rules specifying second minimum geometric constraints allowable for features in the second memory region; wherein step (b) includes the following steps: (b1) checking geometric features of said second type of circuit region against said first set of design rules; and (b2) identifying any errors triggered by said geometric features of said second type of circuit region, said errors corresponding to instances where said geometric figures do not comply with said first set of design rules; and (b3) modifying at least some of said first minimum geometric constraints in said first set of design rules in response to any errors identified in step (b2); wherein said second set of design rules is derived from some of said first minimum geometric constraints and others of said first minimum geometric constraints that have been modified to accommodate characteristics of said geometric features as they may be found in said second type of circuit region; wherein at least some of said first minimum geometric constraints and said second minimum geometric constraints are different; and further wherein steps (b1) to (b3) are repeated to generate a third set of design rules for a third type of circuit region; and further wherein said first set of design rules and said second set of design rules are in a form suitable for use by a design rule checking software application.