Symmetric Multi-Processing System Utilizing a Dmac to Allow Address Translation for Attached Processors

1. A system, comprising: (a) a shared memory; and (b) two or more processing elements coupled to said shared memory, wherein two or more of said processing elements comprise: (1) a processing unit, wherein said processing unit comprises a first address translation mechanism; (2) a direct memory access controller coupled to said processing unit, wherein said direct memory access controller comprises a second address translation mechanism; and (3) at least one attached processing unit coupled to said direct memory access controller, wherein said at least one attached processing unit does not comprise an address translation mechanism.

2. The system as recited in claim 1 , wherein said first and said second address translation mechanism translate a range of virtual addresses to a corresponding range of physical addresses.

3. The system as recited in claim 2 , wherein said corresponding range of physical addresses are pinned.

4. The system as recited in claim 1 , wherein said first and said second address translation mechanism comprise a first and a second translation lookaside buffer, respectively.

5. The system as recited in claim 4 , wherein said first translation lookaside buffer and said second translation lookaside buffer comprise matching pages.

6. The system as recited in claim 4 , wherein said first translation lookaside buffer and said second translation lookaside buffer contain matching translations.

7. The system as recited in claim 1 further comprising: a translation consistency mechanism coupled to said first and said second address translation mechanism.

8. The system as recited in claim 7 , wherein said translation consistency mechanism controls said first and second address translation mechanism to translate a range of virtual addresses to a corresponding range of physical addresses.

9. The system as recited in claim 7 , wherein said first and said second address translation mechanism comprise a first and a second translation lookaside buffer, respectively.

10. The system as recited in claim 9 , wherein said translation consistency mechanism effectuates matching pages in said first translation lookaside buffer and in said second translation lookaside buffer.

11. The system as recited in claim 9 , wherein said translation consistency mechanism effectuates matching translations in said first translation lookaside buffer and in said second translation lookaside buffer.