Speculative Counting of Performance Events with Rewind Counter

1. A control circuit for use with a microprocessor having a speculative processing unit and a performance monitoring unit, said control circuit comprising: a rewind register having a first rewind register value, said rewind register logically connected to a first performance monitoring counter in said performance monitoring unit, wherein said first performance monitoring counter accumulates a count of delay cycles experienced by said microprocessor during a load from a memory, and wherein said first rewind register value describes an accumulated number of delay cycles that are experienced by said microprocessor before executing a speculative operation; and an intelligence circuitry, logically connected to said speculative processing unit and said first performance monitoring counter, wherein in response to said speculative operation being erroneous, said said first performance monitoring counter is overwritten with said first rewind register value from said rewind register.

2. The control circuit described in claim 1 , wherein said speculative processing unit is a branch prediction unit.

3. The control circuit described in claim 1 , wherein said performance monitoring unit includes a second performance monitoring counter, and wherein said second performance monitoring counter accumulates a count of processor cycles experienced by said microprocessor, and wherein said rewind register contains a second rewind register value that describes an accumulated number of processor cycles that are experienced by said microprocessor before executing said speculative operation, and wherein in response to said speculative operation being erroneous, said second performance monitoring counter is overwritten with second rewind register value from said rewind register.

4. The control circuit described in claim 1 , wherein said performance monitoring unit includes a third performance monitoring counter, and wherein said third performance monitoring counter accumulates a count of instructions completed by said microprocessor, and wherein said rewind register contains a third rewind register value that describes an accumulated number of instructions that are completed by said microprocessor before executing said speculative operation, and wherein in response to said speculative operation being erroneous, said third performance monitoring counter is overwritten with said third rewind register value from said rewind register.

5. A method for use in a microprocessor having a speculative processing unit and a performance monitoring unit, said method comprising: storing a first rewind register value in a rewind register, wherein said rewind register is logically connected to a first performance monitoring counter in a performance monitoring unit, and wherein said first performance monitoring counter accumulates a count of delay cycles experienced by a microprocessor during a load from a memory, and wherein said first rewind register value describes an accumulated number of delay cycles that are experienced by said microprocessor before executing a speculative operation; and in response to said speculative operation being erroneous, overwriting said first performance monitoring counter with said first rewind register value from said rewind register.

6. The method of claim 5 , wherein said speculative processing unit is a branch prediction unit.

7. The method of claim 5 , further comprising: accumulating, in a second performance monitoring counter in said performance monitoring unit, a count of processor cycles experienced by said microprocessor; storing a second rewind register value in said rewind register, wherein said second rewind register value describes an accumulated number of processor cycles that are experienced by said microprocessor before executing said speculative operation; and in response to said speculative operation being erroneous, overwriting said second performance monitoring counter with said second rewind register value from said rewind register.

8. The method of claim 5 , further comprising: accumulating, in a third performance monitoring counter in said performance monitoring unit, a count of instructions completed by said microprocessor; storing a third rewind register value in said rewind register, wherein said third rewind register value describes an accumulated number of instructions that are completed by said microprocessor before executing said speculative operation; and in response to said speculative operation being erroneous, overwriting said third performance monitoring counter with said third rewind register value from said rewind register.