6951003

Placing Cells of an Ic Design Using Partition Preconditioning

PublishedSeptember 27, 2005
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
21 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A computer implemented method for placing of circuit elements of an integrated circuit design comprising: grouping cells of an integrated circuit design to model curvature of an objective function, said grouping producing a plurality of cell clusters; estimating curvature of said objective function for each of said cell clusters; describing interactions between said cell clusters as a relation; determining a set of preconditioning values which achieves a separation of variables of said relation; scaling the variables of the objective function with the set of preconditioning values such that changing each variable of the objective function affects the objective function by a comparable amount to the preconditioning value within the set of preconditioning values; and placing said circuit elements using said preconditioning values.

2

2. The method as described in claim 1 wherein said grouping comprises merging cells based upon a minimum cell area.

3

3. The method as described in claim 1 wherein said plurality of cell clusters is modeled in a data structure in computer memory as a tree structure.

4

4. The method as described in claim 3 wherein said tree structure is a binary tree.

5

5. The method as described in claim 1 wherein said relation is quadratic.

6

6. The method as described in claim 5 wherein said interactions between said cell clusters are modeled in a data structure in computer memory as springs.

7

7. The method as described in claim 5 wherein placing cell circuit elements involves a calculation of a wire length comprising a weighting factor.

8

8. The method as described in claim 1 wherein said relation is not quadratic.

9

9. The method as described in claim 1 further comprising transforming variables to a preconditioning domain.

10

10. A system comprising: a processor coupled to a bus; a memory coupled to said bus and wherein said memory contains instructions that when executed implement a method comprising preconditioning a placing of circuit elements of an integrated circuit design, grouping cells of an integrated circuit design to model curvature of an objective function, said grouping producing a plurality of cell clusters; estimating curvature of said objective function for each of said cell clusters; describing interactions between said cell clusters as a relation; determining a set of preconditioning values which achieves a separation of variables of said relation; and scaling the variables of the objective function with the set of preconditioning values such that changing each variable of the objective function affects the objective function by a comparable amount to a preconditioning value within the set of preconditioning values.

11

11. The system as described in claim 10 wherein said grouping comprises merging cells based upon a minimum cell area.

12

12. The system as described in claim 10 wherein said plurality of cell clusters is modeled as a tree structure.

13

13. The system as described in claim 12 wherein said tree structure is a binary tree.

14

14. The system as described in claim 10 wherein said relation is quadratic.

15

15. The system as described claim 14 wherein said interactions between said cell clusters are modeled as springs.

16

16. The system as described in claim 10 wherein placing cell circuit elements involves a calculation of a wire length comprising a weighting factor.

17

17. The system as described in claim 10 wherein said relation is not quadratic.

18

18. The system as described in claim 10 further comprising transforming variables to a preconditioning domain.

19

19. The system as described in claim 10 further comprising placing said cells using said preconditioning values.

20

20. A computer-readable medium having computer-readable program code embodied therein for causing a computer system to perform a method; said method comprising preconditioning a placing of circuit elements of an integrated circuit design grouping cells of an integrated circuit design to model curvature of an objective function, said grouping producing a plurality of cell clusters; estimating curvature of said objective function for each of said cell clusters; describing interactions between said cell clusters as a relation; determining a set of preconditioning values which achieves a separation of variables of said relation; and scaling the variables of the objective function with the set of preconditioning values such that changing each variable of the objective function affects the objective function by a comparable amount to the preconditioning value within the set of preconditioning values.

21

21. The computer-readable medium of claim 20 wherein said method further comprises placing said cells using said preconditioning values.

Patent Metadata

Filing Date

Unknown

Publication Date

September 27, 2005

Inventors

Troy W. Barbee III
William Clark Naylor JR.
Ross Alexander Donelly

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Cite as: Patentable. “PLACING CELLS OF AN IC DESIGN USING PARTITION PRECONDITIONING” (6951003). https://patentable.app/patents/6951003

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PLACING CELLS OF AN IC DESIGN USING PARTITION PRECONDITIONING — Troy W. Barbee III | Patentable