Low Power, Up Full Swing Voltage CMOS Bus Receiver

1. A CMOS bus receiver for converting a first voltage swing input signal at an input node to a second voltage swing output signal, having a greater voltage swing than the first voltage swing, at an output node, comprising: a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node; a third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors; a fifth MOS transistor connected in series by a source and drain with a diode between the first side of the power supply and the input node, a gate of the fourth MOS transistor being connected to the common connection node of the fifth MOS transistor and the diode; and an inverter having an input connected to the output node and an output connected to a gate of the fifth MOS transistor.

2. A CMOS bus receiver as in claim 1 , wherein the diode comprises a sixth MOS transistor having a gate connected to a source or drain thereof.

3. A CMOS bus receiver as in claim 1 , wherein the inverter comprises: a sixth and a seventh MOS transistor connected in series by a source and drain between the first side of the power supply and the gate of the fifth MOS transistor, a gate of the sixth MOS transistor, being connected to the first side of the power supply, and a gate of the seventh MOS transistor being connected to the output node; and an eighth MOS transistor connected by a source and drain between the gate of the fifth transistor and the second side of the power supply, and having a gate connected to the output node.

4. A CMOS bus receiver as in claim 1 , wherein the inverter comprises: a sixth MOS transistor connected by a source and drain between the first side of the power supply and the gate of the fifth MOS transistor, and having a gate connected to the common connection node of the third and fourth MOS transistors; and a seventh MOS transistor connected by a source and drain between the gate of the fifth transistor and the second side of the power supply, and having a gate connected to the output node.