Interleaved Processing System for Processing Frames Within a Network Router

1. A system for processing a packet, wherein said packet includes a source address bit pattern and a destination address bit pattern that are each processed by a task processor in accordance with a data tree, said data tree including a plurality of nodes linked by branches wherein an instruction that is associated with each node is utilized for selecting a next branch in accordance with said source address bit pattern or said destination address bit pattern, said system comprising: a first bank of registers for loading an instruction to be executed by said task processor at one or more nodes of said data tree in accordance with said source address bit pattern; a second bank of registers for loading an instruction to be executed by said task processor at one or more nodes of said data tree in accordance with said destination address bit pattern; instruction load means for loading said first and second bank of registers; and a task scheduler that enables said instruction load means to load a next instruction to said first bank of registers and enables said second bank of registers to transfer an instruction loaded therein for processing by said task processor during a first time cycle domain, wherein said task scheduler further enables said instruction load means to load a next instruction to said second bank of registers and enables said first bank of registers to transfer an instruction loaded therein for processing by said task processor during a second time cycle domain that is interleaved in an alternating manner with said first time cycle domain.

2. The system of claim 1 , wherein said task scheduler includes a clock signal generator that generates said interleaved first and second time cycle domains in an alternating series of rising edges and falling edges.

3. The system of claim 1 , further comprising an address register for storing an address of a next instruction to be loaded into either said first bank of registers or said second bank of registers from a memory device before being executed by said task processor.

4. The system of claim 3 , wherein said address register further comprises a counter for incrementing said address of the next instruction in response to a dual size instruction.

5. The system of claim 3 , wherein said memory includes instructions to be executed by said task processor.

6. The system of claim 5 , wherein said memory further comprises a first memory area containing single size instructions and a second memory area containing dual size instructions.

7. The system of claim 1 , further comprising at least one temporary register for storing information from said task processor between two consecutive processing time cycles when such a processing lasts more than one time cycle.

8. The system of claim 1 , further comprising a 1-bit state register for each of said first and second bank of registers, said 1-bit state register being set when said processing lasts more than one time cycle.

9. A method for processing a packet, wherein said packet includes a source address bit pattern and a destination address bit pattern that are each processed by a task processor in accordance with a data tree, said data tree including a plurality of nodes linked by branches wherein an instruction that is associated with each node is utilized for selecting a next branch in accordance with said source address bit pattern or said destination address bit pattern, said method comprising: (a) loading into a first bank of registers a next instruction to be executed by said task processor at one or more nodes of said data tree in accordance with said source address bit pattern; (b) transferring an instruction from a second bank of registers to be processed by said task processor; (c) loading into said second bank of registers a next instruction to be executed by said task processor at one or more nodes of said data tree in accordance with said destination address bit pattern; (d) transferring an instruction from said first bank of registers to be processed by said task processor; and (e) scheduling steps (a) and (b) to be coincidentally performed during a first time cycle domain and steps (c) and (d) to be coincidentally performed during a second time cycle domain, wherein said second time cycle domain is interleaved in an alternating manner with said first time cycle domain.

10. The method of claim 9 , further comprising generating said first and second time cycle domains in an alternating series of rising edges and falling edges.

11. The method of claim 9 , further comprising storing an address of a next instruction to be loaded into either said first bank of registers or said second bank of registers from a memory device before being executed by said task processor.

12. The method of claim 11 , further comprising: loading said address of said next instruction from said task processor into said first or second bank of registers; transferring said address from said bank of registers to said address register; reading said address from said address register; and fetching said next instruction from said memory in response to said reading step.

13. The method of claim 11 , further comprising incrementing said address of the next instruction in response to a dual size instruction.

14. The method of claim 13 , further comprising: loading a dual size instruction into either said first bank of registers or said second bank of registers; interrupting said loading step during one time cycle if said loading requires two time cycles; and during said time cycle during which said loading is interrupted, loading an instruction into the other of said first or second bank of registers.

15. The method of claim 13 , further comprising: processing a dual size instruction utilizing said task processor; interrupting said processing step during one time cycle if such a processing requires two time cycles; and during said time cycle during which said processing is interrupted, executing an instruction provided by the other of said first or second bank of registers.

16. The method of claim 9 , further comprising storing information from said task processor between two consecutive processing time cycles when such a processing lasts more than one time cycle within at least one temporary register.