Microprocessor Cache Design Initialization

1. In a system including a representation of a cache in a microprocessor design, a computer-implemented method for initializing the cache representation, the method comprising steps of: (A) identifying a first cache initialization record comprising a first cache entry reference and a first initial cache entry value, the first cache entry reference comprising a first address identifier and a first way identifier; (B) determining whether the first way identifier specifies any way in the cache; and (C) if the first way identifier is determined to specify a first way in the cache, performing steps of: (1) identifying a cache entry, in the cache representation, specified by the first address identifier and the first way identifier; and (2) initializing the cache entry identified in step (C) (1) with the first initial cache entry value.

2. The method of claim 1 , further comprising a step of: (D) storing the first cache initialization record in a deferred initialization list if the first way identifier is determined not to specify any way in the cache.

3. The method of claim 1 , further comprising a step of: (D) performing the steps (A), (B), and (C) for each of a plurality of cache initialization records.

4. The method of claim 3 , further comprising a step of: (E) storing the first cache initialization record in a deferred initialization list if the first way identifier is determined not to specify any way in the cache; and wherein the step (D) comprises a step of performing the steps (A), (B), (C), and (E) for each of the plurality of cache initialization records.

5. The method of claim 4 , further comprising a step of: (F) for each of a plurality of cache initialization records in the deferred initialization list, performing steps of: (1) identifying a second cache initialization record comprising a second cache entry reference and a second initial cache entry value, the second cache entry reference comprising a second address identifier and a second way identifier; (2) determining whether the second way identifier specifies any way in the cache; (3) if the second way identifier is determined to specify a second way in the cache, performing steps of: (i) identifying a cache entry, in the cache representation, specified by the second address identifier and the second way identifier; and (ii) initializing the cache entry identified in step (F) (3) (i) with the second initial cache entry value; and (4) if it is determined that the second way identifier does not specify any way in the cache, performing steps of: (i) selecting a third way identifier such that the second address identifier and the third way identifier specify an un-initialized cache entry in the cache representation; and (ii) initializing the un-initialized cache entry with the second initial cache entry value.

6. The method of claim 5 , wherein the step (F) (4) (i) comprises steps of: (a) randomly selecting the third way identifier; (b) determining whether the second address identifier and the third way identifier specify an initialized cache entry in the cache representation; and (c) repeating steps (F) (4) (i) (a) and (F) (4) (i) (b) when it is determined that the second address identifier and the third way identifier specify an initialized cache entry in the cache representation.

7. The method of claim 3 , wherein the system further comprises a test case file including the plurality of cache initialization records, and wherein the step (D) comprises a step of sequentially reading the plurality of cache initialization records from the test case file.

8. The method of claim 1 , wherein the step (B) comprises a step of determining whether the first way identifier comprises a null value.

9. A system comprising: a representation of a cache in a microprocessor design; identifying means for identifying a first cache initialization record comprising a first cache entry reference and a first initial cache entry value, the first cache entry reference comprising a first address identifier and a first way identifier; first determining means for determining whether the first way identifier specifies any way in the cache; and initialization means for performing the following steps if the first way identifier is determined to specify a first way in the cache: (1) identifying a first cache entry, in the cache representation, specified by the first address identifier and the first way identifier; and (2) initializing the first cache entry with the first initial cache entry value.

10. The system of claim 9 , further comprising: means for storing the first cache initialization record in a deferred initialization list if the first way identifier is determined not to specify any way in the cache.

11. The system of claim 9 , further comprising: iteration means for applying the identifying means, the first determining means, and the initialization means to each of a plurality of cache initialization records.

12. The system of claim 11 , further comprising: storage means for storing the first cache initialization record in a deferred initialization list if the first way identifier is determined not to specify any way in the cache; and wherein the iteration comprises means for applying the identifying means, the first determining means, the initialization means, and the storage means to each of the plurality of cache initialization records.

13. The system of claim 12 , further comprising, for each of a plurality of cache initialization records in the deferred initialization list: means for identifying a second cache initialization record comprising a second cache entry reference and a second initial cache entry value, the second cache entry reference comprising a second address identifier and a second way identifier; means for determining whether the second way identifier specifies any way in the cache; means for performing the following steps if the second way identifier is determined to specify a second way in the cache: (1) identifying a second cache entry, in the cache representation, specified by the second address identifier and the second way identifier; and (2) initializing the second cache entry with the second initial cache entry value; and means for performing the following steps if it is determined that the second way does not specify any way in the cache: (1) selecting a third way identifier such that the second address identifier and the third way identifier specify an un-initialized cache entry in the cache representation; and (2) initializing the un-initialized cache entry with the second initial cache entry value.

14. The system of claim 13 , wherein the means for selecting the third way identifier comprises: random selection means for randomly selecting the third way identifier; second determining means for determining whether the second address identifier and the third way identifier specify an initialized cache entry in the cache representation; and means for applying the random selection means and the second determining means again when it is determined that the second address identifier and the third way identifier specify an initialized cache entry in the cache representation.

15. The system of claim 11 , wherein the system further comprises a test case file including the plurality of cache initialization records, and wherein the iteration means comprises means for sequentially reading the plurality of cache initialization records from the test case file.

16. The system of claim 9 , wherein the first determining means comprises means for determining whether the first way identifier comprises a null value.