Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer capable of playing real time applications comprising: a processing circuit configured to operate in a first power state, a second power state, and a third power state, said processing circuit consuming less power in said second power state than in said first power state, and said processing circuit consuming less power in said third power state than in said second power state; and a real time subsystem coupled to said processing circuit, said real time subsystem comprising a buffer, said buffer configured to store data and output said data to an output device for playing said real time applications thereby enabling said processing circuit to enter said third power state while said buffer is outputting said data.
2. The computer of claim 1 , wherein said first power state is a full power state, said second power state is a light sleep state, and said third power state is a deep sleep state, said light sleep state further comprising a first light sleep state and a second light sleep state, wherein said processing circuit consumes less power in said second light sleep state than in said first light sleep state, and wherein said buffer stores said data while said processing circuit is in said full power state or said first light sleep state.
3. The computer of claim 2 , wherein said full power state is state C 0 , said first light sleep state is state C 1 , said second light sleep state is state C 2 , and said deep sleep state is state C 3 .
4. The computer of claim 1 , wherein said real time application subsystem is a video subsystem or an audio subsystem.
5. The computer of claim 1 , wherein said buffer is a FIFO buffer.
6. A real time subsystem comprising: a buffer configured to store data for use in said real time subsystem enabling a processing circuit of a computer to enter a deep sleep state while said computer is running said real time subsystem.
7. The real time subsystem of claim 6 , wherein said real time subsystem is a video subsystem or audio subsystem.
8. A method of conserving power in a computer while playing a real time application comprising the steps of: reading a storage medium of data for use in said real time application; processing said data in a processing circuit configured to operate in a first power state, a second power state, and a third power state, said processing circuit consuming less power in said second power state than in said first power state, and said processing circuit consuming less power in said third power state than in said second power state; storing said data in a buffer; outputting said data from said buffer to a real time application output device; and placing said processing circuit in said third power state while said buffer is outputting said stored data.
9. The method of claim 8 , wherein said first power state is a full power state, said second power state is a light sleep state, and said third power state is a deep sleep state, said light sleep state further comprising a first light sleep state and a second deep light state, wherein said processing circuit consumes less power in said second light sleep state than in said first light sleep state, and wherein said storing occurs when said processing circuit is in said full power state.
10. The method of claim 9 , wherein said full power state is state C 0 , said first light sleep state is state C 1 , said second light sleep state is state C 2 , and said deep sleep state is state C 3 .
11. The method of claim 8 , wherein said storing step is completed when said buffer reaches a predetermined full level data condition, and said processing circuit is woken up from said third power state when said buffer reaches a predetermined low level data condition.
12. The method of claim 11 , wherein said first power state is a full power state, said second power state is a light sleep state, and said third power state is a deep sleep state, said light sleep state further comprising a first deep light state and a second light sleep state, wherein said processing circuit consumes less power in said second light sleep state than in said first light sleep state, and when said processing circuit is said woken up, said processing circuit enters into said full power state.
13. The method of claim 12 , wherein said full power state is state C 0 , said first light sleep state is state C 1 , said second light sleep state is state C 2 , and said deep sleep state is state C 3 .
14. A method of conserving power in a computer where at least one device has direct access to system memory comprising the steps of: flushing cache memory of a processing circuit to said system memory of said computer, wherein said processing circuit is configured to operate in a first power state, a second power state, and a third power state, said processing circuit consuming less power in said second power state than in said first power state, and said processing circuit consuming less power in said third power state than in said second power state; placing said processing circuit in said third power state; and maintaining a first device power state in said at least one device, wherein said at least one device is configured to operate in said first device power state, a second device power state, and a third device power state, said device consuming less power in said second device power state than in said first device power state, and said device consuming less power in said third device power state than in said second device power state.
15. The method of claim 14 , wherein said first power state is a full power state, said second power state is a light sleep state, and said third power state is a deep sleep state, said light sleep state further comprising a first light sleep state and a second light sleep state, wherein said processing circuit consumes less power in said second light sleep state than in said first light sleep state.
16. The method of claim 15 , wherein said full power state is state C 0 , said first light sleep state is state C 1 , said second light sleep state is state C 2 , and said deep sleep state is state C 3 .
17. The method of claim 14 , wherein said first device power state is a full device power state, said second device power state is a light sleep device state, and said third device power state is a deep sleep device state, said light sleep device state further comprising a first device light sleep state and a second device light sleep state, wherein said device consumes less power in said second device light sleep state than in said first device light sleep state.
18. The method of claim 17 , wherein said full device power state is state D 0 , said first device light sleep state is state D 1 , said second device light sleep state is state D 2 , and said deep sleep device state is state D 3 .
19. A computer capable of playing real time applications comprising: a processing circuit; an output device coupled to said processing circuit via a bus; and a real time subsystem coupled to said processing circuit via said bus, said real time subsystem comprising a buffer, said buffer configured to store data and output said data to said output device for playing said real time applications thereby enabling said processing circuit to enter a deep sleep state while said buffer is outputting said data.
Unknown
November 22, 2005
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