Integrated Circuit Device

1. An integrated circuit comprising: a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.

2. The integrated circuit of claim 1 , wherein: the first circuit further receives, in a multiplexed format, control information that specifies a read operation, and address information specifying a location within the memory array for the read operation; and the second circuit includes a plurality of input receivers to receive, after a predetermined number of clock cycles of the external clock signal transpire, read data corresponding to the read operation, wherein each input receiver of the plurality of input receivers receives two bits of the data during a single clock cycle of the external clock signal.

3. The integrated circuit of claim 2 , wherein each input receiver of the plurality of input receivers includes a first input sampler and a second input sampler, wherein each of the first and second input samplers samples one bit of the two bits of data sampled by the input receiver during a single clock cycle of the external clock signal.

4. The integrated circuit of claim 2 , wherein the second circuit includes output drivers to output a value, to the external memory device, that is representative of an amount of data to be written to the memory array of the external memory device.

5. The integrated circuit device of claim 1 , wherein the second circuit includes output drivers to output a value, to the external memory device, that is representative of the number of clock cycles of the external clock signal.

6. The integrated circuit device of claim 1 , wherein the plurality of output drivers of the second circuit includes output drivers to forward the address information to the external memory device.

7. The integrated circuit device of claim 1 , wherein the plurality of output drivers output the control information and the address information to the external memory device in a multiplexed format.

8. The integrated circuit device of claim 1 , wherein the first circuit receives the control information and the address information in a packet format, and wherein the first circuit includes a receiver to receive a signal that indicates the beginning of a packet that includes the control information and the address information.

9. The integrated circuit device of claim 1 , further including a third circuit to generate a first internal clock signal, wherein each output driver of the plurality of output drivers outputs the data using the first internal clock signal, wherein the third circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal.

10. The integrated circuit device of claim 9 , wherein the third circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the plurality of output drivers further outputs a first portion of the data using the first internal clock signal and the plurality of output drivers outputs a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

11. An integrated circuit device, comprising: first receivers to receive address and control in a multiplexed format such that at least one receiver of the receivers receives a portion of both the address information and the control information, wherein the address information and the control information correspond to a read operation for a memory device; output drivers to output an operation code and a read address, wherein the operation code and the read address are based on the address information and the control information; and second receivers to receive read data, corresponding to the read operation, after a programmed number of clock cycles of an external clock signal, wherein each receiver of the second receivers receives two bits of the read data during a single clock cycle of the external clock signal.

12. The integrated circuit device of claim 11 , wherein the programmed number of clock cycles is indicated by a value stored in a register, wherein the first receivers receive the value.

13. The integrated circuit of claim 11 , wherein each receiver of the second receivers includes a first sampler and a second sampler, wherein each of the first and second samplers samples one bit of the two bits of the read data received during the single clock cycle of the external clock signal.

14. The integrated circuit device of claim 11 , wherein the output drivers output the operation code and the address information to an external memory device, wherein the address information identifies a memory location within the external memory device.

15. The integrated circuit device of claim 11 , wherein the output drivers output the operation code and the read address in a packet format, and wherein the output drivers include an output driver to output a signal that indicates the beginning of a packet that includes the operation code and the read address.

16. The integrated circuit device of claim 11 , wherein the first receivers receives the control information and the address information in a packet format, and wherein the first receivers includes a receiver to receive a signal that indicates the beginning of a packet that includes the control information and the address information.

17. The integrated circuit device of claim 11 , further including a circuit to generate a first internal clock signal, wherein the output drivers output the data using the first internal clock signal, wherein the circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal.

18. The integrated circuit device of claim 17 , wherein the circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the output drivers further output a first portion of the data using the first internal clock signal and the output drivers output a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

19. The integrated circuit device of claim 11 , wherein the first receivers receive the address information from a memory controller and the output drivers output the operation code and the read address to a memory device, wherein the memory device outputs the read data in response to the operation code.

20. The integrated circuit device of claim 11 , where in each output driver of the output drivers outputs two consecutive bits of the address information during a single clock cycle of the external clock signal.

21. An integrated circuit comprising: a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information.

22. The integrated circuit of claim 21 wherein: the first circuit further receives, in a multiplexed format, control information that specifies a read operation, and address information .specifying a location within the memory array for the read operation; and the second circuit includes a plurality of input receivers to receive, after a predetermined number of clock cycles of the external clock signal transpire, read data corresponding to the read operation, wherein each input receiver of the plurality of input receivers receives two bits of the data during a single clock cycle of the external clock signal.

23. The integrated circuit of claim 22 , wherein each input receiver of the plurality of input receivers includes a first input sampler and a second input sampler, wherein each of the first and second input samplers samples one bit of the two bits of data sampled by the input receiver during a single clock cycle of the external clock signal.

24. The integrated circuit of claim 22 , wherein the second circuit includes output drivers to output a value that is representative of an amount of data to be written to the memory array of the external memory device.

25. The integrated circuit device of claim 21 , wherein the second circuit includes output drivers to output a value to the external memory device, wherein the value is representative of the number of clock cycles of the external clock signal.

26. The integrated circuit device of claim 21 , wherein the plurality of output drivers of the second circuit includes output drivers to forward the address information to the external memory device.

27. The integrated circuit device of claim 21 , wherein the plurality of output drivers output the control information and the address information to the external memory device in a multiplexed format.

28. The integrated circuit device of claim 21 , wherein the first circuit receives the control information and the address information in a packet format, and wherein the first circuit includes a receiver to receive a signal that indicates the beginning of a packet that includes the control information and the address information.

29. The integrated circuit device of claim 21 , further including a third circuit to generate a first internal clock signal, wherein each output driver of the plurality of output drivers of the second circuit outputs the data using the first internal clock signal, wherein the third circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal.

30. The integrated circuit device of claim 29 , wherein the third circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the plurality of output drivers further outputs a first portion of the data using the first internal clock signal and the plurality of output drivers outputs a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

31. A method of operation of an integrated circuit device, the method comprising: receiving, in a multiplexed format, control information and address information, the control information specifying a write operation to an external memory device, and the address information specifying a location within a memory array of the memory device; outputting an operation code that specifies the write operation; and outputting data in response to the control information, after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is to be written to the memory array during the write operation.

32. The method of claim 31 , further including: receiving control information specifying a read operation; outputting an operation code that corresponds to the control information, wherein the memory device outputs read data in response to the operation code; and sampling the read data, output by the first memory device, after a delay time transpires, wherein the sampling is done by input receivers on the integrated circuit device such that each input receiver samples two bits of the read data during a single clock cycle of the external clock signal.

33. The method of claim 31 , further including outputting a value, to the memory device, that is representative of the predetermined number of clock cycles of the external clock signal.

34. The method of claim 31 , further including: receiving a value that is representative of the predetermined number of clock cycles of the external clock signal; and outputting the value to the memory device.

35. The method of claim 31 , further including outputting a value, to the memory device, that is representative of an amount of the data that the first memory device receives from the integrated circuit device.

36. The method of claim 31 , wherein outputting data is done by output drivers on the integrated circuit device such that each output driver outputs two bits of the data for during a single clock cycle of the external clock signal.

37. The method of claim 31 , further including forwarding the address information to the first memory device.

38. The method of claim 31 , further including forwarding the control information to the first memory device.

39. The method of claim 31 , further including: generating a first internal clock signal using the external clock signal; and controlling a timing relationship between the first internal clock signal and the external clock signal using a feedback loop; wherein outputting data includes outputting data using the first internal clock signal.

40. The method of claim 39 , further including generating a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein outputting data includes outputting the data using the second internal clock signal.

41. An integrated circuit device comprising: means for receiving control information and address information in a multiplexed format, the control information specifying a write operation to an external memory device, and the address information specifying a memory location in the external memory device for the write operation; and means for outputting data to the memory device after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is to be written to the memory array during the write operation.