On-Chip Power-Ground Inductance Modeling Using Effective Self-Loop-Inductance

1. A method comprising: calculating effective self loop inductance for on-chip power wire segments and on-chip ground wire segments in an integrated circuit (IC) design, wherein calculating effective self-loop inductance is performed under an assumption that a current loop exists from each of the power or ground wire segments to its nearest respective ground or power wire segments with a total cross-sectional area of wire segments in the current loop equal to 1–5 times cross-sectional area of one or more of its nearest wire segments; modeling each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; and simulating noise of the IC design using the self-loop inductors to represent associated wire segments.

2. The method defined in claim 1 wherein the noise comprises Delta-I noise.

3. The method defined in claim 1 wherein the design is for a wire-bumped chip.

4. The method defined in claim 1 wherein the design is for a periphery-bumped chip.

5. A method comprising: calculating effective self loop inductance for on-chip power wire segments and on-chip ground wire segments in an integrated circuit (IC) design, wherein calculating effective self-loop inductance is performed under an assumption that a current loop exists from each of the power or ground wire segments to its nearest respective ground or power plane or mesh at a package specified in the IC design with a total cross-sectional area of wire segments in the current loop equal to 0.2–2 times cross-sectional area of the one or more of its nearest wire segments; modeling each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; and simulating noise of the IC design using the self-loop inductors to represent associated wire segments.

6. The method defined in claim 5 wherein the IC design is for an area-bumped chip.

7. The method defined in claim 5 wherein the IC design is for an C4 chip.

8. A method comprising: calculating effective self loop inductance for on-chip power wire segments and on-chip ground wire segments in an integrated circuit (IC) design; modeling each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; simulating noise of the IC design using the self-loop inductors to represent associated wire segments; partitioning at least one of the power or ground wire segments into a plurality of sub- segments; calculating effective self-loop inductance for each of the plurality of sub-segments; and modeling the at least one wire segment via a serial combination of the calculated effective self-loop inductances of the plurality of sub-segments.

9. An apparatus comprising: means for calculating effective self loop inductance for on-chip power and ground wire segments in an integrated circuit (IC) design, wherein means for calculating effective self-loop inductance is performed under an assumption that a current loop exists from each of the power or ground wire segments to its nearest respective ground or power wire segments specified in the IC design with a total cross-sectional area of wire segments in the current loop equal to 1–5 times cross-sectional area of one or more of its nearest wire segments; means for modeling each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; and means for simulating noise of the IC design using the self-loop inductors to represent associated wire segments.

10. The apparatus defined in claim 9 wherein the noise comprises Delta-I noise.

11. The apparatus defined in claim 9 wherein the design is for a wire-bumped chip.

12. The apparatus defined in claim 9 wherein the design is for a periphery-bumped chip.

13. An apparatus comprising: means for calculating effective self loop inductance for on-chip power and ground wire segments in an integrated circuit (IC) design, wherein means for calculating effective self-loop inductance is performed under an assumption that a current loop exists from each of the power or ground wire segments to its nearest respective ground or power planes or mesh at a package specified in the IC design with a total cross-sectional area of wire segments in the current loop equal to 02–2 times cross-sectional area of its nearest wire segments; means for modeling each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; and means for simulating noise of the IC design using the self-loop inductors to represent associated wire segments.

14. The apparatus defined in claim 13 wherein the IC design is for an area-bumped chip.

15. The apparatus defined in claim 13 wherein the IC design is for an C4 chip.

16. An apparatus comprising: means for calculating effective self loop inductance for on-chip power and ground wire segments in an integrated circuit (IC) design; means for modeling each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; means for simulating noise of the IC design using the self-loop inductors to represent associated wire segments; means for partitioning at least one of the wire segments into a plurality of sub-segments; means for calculating effective self-loop inductance for each of the plurality of sub- segments; and means for modeling the at least one wire segment via a serial combination of the calculated effective self-loop inductances of the plurality of sub-segments.

17. An article of manufacture comprising a computer readable medium having computer readable code stored thereon, which, when executed by a system, causes the system to: calculate effective self loop inductance for on-chip power and ground wire segments in an integrated circuit (IC) design, wherein calculating effective self-loop inductance is performed under an assumption that a current loop exists from each of the power or ground wire segments to its nearest respective ground or power wire segments specified in the IC design with a total cross-sectional area of wire segments in the current loop equal to 1-5 times cross-sectional area of one or more of its nearest wire segments; model each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; and simulate noise of the IC design using the self-loop inductors to represent associated wire segments.

18. The article defined in claim 17 wherein the noise comprises Delta-I noise.

19. The article defined in claim 17 wherein the design is for a wire-bumped chip.

20. The article defined in claim 17 wherein the design is for a periphery-bumped chip.

21. An article of manufacture comprising a computer readable medium having computer readable code stored thereon, which, when executed by a system, causes the system to: calculate effective self loop inductance for on-chip power and ground wire segments in an integrated circuit (IC) design, wherein calculating effective self-loop inductance is performed under an assumption that a current loop exists from each of the power or ground wire segments to its nearest respective ground or power planes or mesh at a package specified in the IC design with a total cross-sectional area of wire segments in the current loop equal to 0.2–2 times cross-sectional area of the one or more of its nearest wire segments; model each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; and simulate noise of the IC design using the self-loop inductors to represent associated wire segments.

22. The article defined in claim 21 wherein the IC design is for an area-bumped chip.

23. The article defined in claim 21 wherein the IC design is for an C4 chip.

24. An article of manufacture comprising a computer readable medium having computer readable code stored thereon, which, when executed by a system, causes the system to: calculate effective self loop inductance for on-chip power and ground wire segments in an integrated circuit (IC) design; model each of the wire segments in the IC design using a self-inductor representing its calculated self-loop inductance of said each wire segment; simulate noise of the IC design using the self-loop inductors to represent associated wire segments; partition at least one of the wire segments into a plurality of sub-segments; calculate effective self-loop inductance for each of the plurality of sub-segments; and model the at least one wire segment via a serial combination of the calculated effective self-loop inductances of the plurality of sub-segments.