Routing Method and Apparatus That Use Diagonal Routes

1. A method of routing a net within a particular region of an integrated circuit (“IC”) layout, the net having a set of pins, the method comprising: a) partitioning the particular IC region into a plurality of sub-regions, wherein each sub-region has the same four-sided shape; and b) identifying a route that connects a set of sub-regions containing the pins of the net, wherein the route has a route edge that is at least partially diagonal, wherein the diagonal edge intersects a corner vertex shared by two diagonally aligned, four-sided sub-regions.

2. The method of claim 1 , wherein identifying the route includes identifying the set of sub-regions that contains the pins of the net.

3. The method of claim 2 , wherein identifying the route further includes using the identified set of sub-regions to retrieve the route from a storage structure.

4. The method of claim 1 , wherein all the sub-regions have the same size.

5. The method of claim 1 , wherein a plurality of paths exist between the sub-regions, wherein a plurality of the paths are diagonal paths, wherein the route traverses at least one of the diagonal paths.

6. The method of claim 5 wherein identifying the route comprises identifying the paths between the sub-regions used by the route.

7. The method of claim 6 , wherein a plurality of the paths are Manhattan paths, wherein the route traverses at least one of the Manhattan paths.

8. The method of claim 1 , wherein a plurality of inter-region edges exist between the sub-regions, wherein a plurality of the inter-region edges between the sub-regions are diagonal inter-region edges, wherein the route intersects at least one of the diagonal inter-region edges.

9. The method of claim 8 , wherein identifying the route comprises identifying the inter-region edges between the sub-regions intersected by the route.

10. The method of claim 9 , wherein a plurality of the inter-region edges between the sub-regions are Manhattan inter-region edges, wherein the route intersects at least one of the Manhattan inter-region edges.

11. The method of claim 1 further comprising: a) computing a cost for the route; b) determining whether to embed the route based on the computed cost.

12. The method of claim 1 , wherein the IC region is the layout of the entire IC.

13. The routing method of claim 1 , wherein the IC region is a portion of the layout of the entire IC.

14. A method of routing a set of nets within a region of an integrated circuit (“IC”) layout, wherein each net includes a set of pins in the region, the method comprising: partitioning the IC region into several sub-regions, wherein each sub-region is a quadrilateral; for each particular net in the region, identifying each sub-region that contains a pin from the set of pins of the particular net, and identifying a route that connects the identified sub-regions for the particular net; wherein some of the identified routes have route edges that are at least partially diagonal, wherein at least one of the diagonal edges connects two diagonally aligned sub-regions by traversing through a corner vertex shared between the two sub-regions.

15. The method of claim 14 , wherein a plurality of paths exist between the sub-regions, and a plurality of the paths are diagonal paths, wherein identifying the route for each particular net comprises identifying the paths used by a set of interconnect lines connecting the sub-regions identified for the particular net, wherein some of the interconnect lines traverse some of the diagonal paths.

16. The method of claim 15 , wherein a plurality of the paths are Manhattan paths, wherein some of the interconnect lines traverse some of the Manhattan paths.

17. The method of claim 15 further comprising embedding each route by storing the identity of the paths used by each route.

18. The method of claim 14 , wherein a plurality of inter-region edges exist between the sub-regions, and a plurality of the inter-region edges are diagonal, wherein identifying the route for each particular net comprises identifying the inter-region edges intersected by a set of interconnect lines connecting the sub-regions identified for the particular net, wherein some of the interconnect lines intersect some of the diagonal inter-region edges.

19. The method of claim 18 , wherein a plurality of the inter-region edges are Manhattan edges, wherein some of the interconnect lines intersect some of the Manhattan inter-region edges.

20. The method of claim 18 further comprising embedding each route by storing the identity of the inter-region edge intersected by each route.

21. The method of claim 14 further comprising: for each particular net in the region, identifying a set of route that connects the identified sub-regions for the particular net; computing costs for the identified routes; selecting one identified route for each net based on the computed costs; embedding the selected route for each net in the region.

22. A computer readable medium comprising a computer program having executable code, the computer program for routing a net within a particular region of an integrated circuit (“IC”) layout, the net having a plurality of pins, the computer program comprising: a) a first set of instructions for partitioning the particular IC region into several sub-regions, wherein each sub-region has the same four-sided shape; and b) a second set of instructions for identifying a route that connects a set of sub-regions containing the pins of the net, wherein the route has a route edge that is at least partially diagonal, wherein the diagonal edge intersects a corner vertex shared by two diagonally aligned, four-sided sub-regions.

23. The computer readable medium of claim 22 , wherein a plurality of paths exist between the sub-regions, and a plurality of the paths are diagonal, wherein the second set of instructions includes a third set of instructions for identifying the paths between the sub-regions used by the route; wherein the route traverses at least one of the diagonal paths.

24. The computer readable medium of claim 22 , wherein a plurality of inter-region edges exist between the sub-regions, and a plurality of the inter-region edges are diagonal, wherein the second set of instructions includes a third set of instructions for identifying the inter-region edges between the sub-regions intersected by the route; wherein the route traverses at least one of the diagonal inter-region edges.

25. The computer readable medium of claim 22 , further comprising: a) a third set of instructions for computing a cost for the route; b) a fourth set of instructions for determining whether to embed the route based on the computed cost.

26. A method of routing a net within a particular region of an integrated circuit (“IC”) layout, the net having a set of pins, the method comprising: a) partitioning the particular IC region into a plurality of sub-regions, wherein the sub-regions have the same shape; and b) identifying a route that connects a set of sub-regions containing the pins of the net, wherein the route has a route edge that is between a first pair of diagonally adjacent sub-regions, wherein the capacity of the route edge is measured from an attribute of another edge that is between a second pair of diagonally adjacent sub-regions, wherein the first and second pair of sub-regions are adjacent to each other.