Dvi Link with Circuit and Method for Test

1. An information transmission link comprising: a transition minimized differential signaling encoder coupled to receive digital data from a plurality of parallel lines to encode the digital data into encoded digital data; a serializer coupled to receive the encoded digital data from the encoder through a plurality of parallel lines to serialize the encoded digital data into encoded and serial digital data; a pseudo-random binary sequence generator circuit to generate test data; a multiplexer coupled to receive the encoded and serial digital data from a first line coupled to the serializer and the test data from a second line coupled to the sequence generator circuit, the multiplexer to transmit the encoded and serial digital data to a transmission medium in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the transmission medium; and wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip.

2. The information transmission link of claim 1 wherein the information transmission link comprises a digital visual interface link.

3. The information transmission link of claim 1 wherein: the digital data comprises digital visual information comprising red data to generate red color in a visual image, green data to generate green color in the visual image, and blue data to generate blue color in the visual image; and the transmission medium comprises one or more conductive wires such as copper cables, or one or more optical fibers, or one or more fiber optic cables.

4. The information transmission link of claim 1 , further comprising a buffer circuit coupled between the multiplexer and the transmission medium to convert the encoded and serial digital data in the normal mode of operation or the test data in the test mode of operation into a differential signal to be transmitted over a pair of differential lines comprising the transmission medium.

5. The information transmission link of claim 1 wherein: the test data comprises pseudo-random binary sequence data that repeats every 2 23 −1 clock cycles; and the sequence generator circuit comprises: twenty three clocked flip flops coupled in series including a first flip flop, twenty one middle flip flops, and a last flip flop, each flip flop comprising a D-type flip flop comprising a D input and a Q output, the Q output of the first flip flop being coupled to the D input of one of the middle flip flops, the D input of the last flip flop being coupled to the Q output of one of the middle flip flops, and the D input of each middle flip flop being coupled to the Q output of one of the flip flops in the sequence generator circuit; an exclusive-NOR gate having a first input coupled to the Q output of the last flip flop, a second input coupled to the Q output of a middle flip flop that is separated from the last flip flop by four of the middle flip flops, and an output coupled to the D input of the first flip flop to provide feedback for the sequence generator circuit; and an inverter having an input coupled to the Q output of the last flip flop and an output to generate the pseudo-random binary sequence data.

6. A information-handling system of the type including the information transmission link of claim 1 , and further comprising: a processor including the encoder, the serializer, the sequence generator circuit, and the multiplexer; a memory device; a display unit having a receiver coupled to receive the encoded and serial digital data to display a visual image generated from the encoded and serial digital data; an input/output subsystem; and a bus coupled to the processor, the memory device, the display unit, and the input/output subsystem, the bus including the transmission medium.

7. A digital visual interface link comprising: a transmitter comprising: a transition minimized differential signaling encoder coupled to receive digital data from a plurality of parallel lines to encode the digital data into encoded digital data; a serializer coupled to receive the encoded digital data from the encoder through a plurality of parallel lines to serialize the encoded digital data into encoded and serial digital data; a pseudo-random binary sequence generator circuit to generate test data; a multiplexer coupled to receive the encoded and serial digital data from a first line coupled to the serializer and the test data from a second line coupled to the sequence generator circuit, the multiplexer to transmit the encoded and serial digital data in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data; and wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip; a transmission medium coupled to the transmitter to transmit the encoded and serial digital data in the normal mode of operation and to transmit the test data in the test mode of operation; and a receiver comprising: a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines; and a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data.

8. The digital visual interface link of claim 7 wherein: the digital data comprises digital visual information comprising red data to generate red color in a visual image, green data to generate green color in the visual image, and blue data to generate blue color in the visual image; the transmission medium comprises one or more conductive wires such as copper cables, or one or more optical fibers, or one or more fiber optic cables; and the receiver further comprises external terminals to be coupled to a bit error rate test set device to couple the test data transmitted over the transmission medium in the test mode of operation to the bit error rate test set device to analyze the test data and determine if there was any corruption of the test data.

9. The digital visual interface link of claim 7 , further comprising a buffer circuit coupled between the multiplexer and the transmission medium to convert the encoded and serial digital data in the normal mode of operation or the test data in the test mode of operation into a differential signal to be transmitted over a pair of differential lines comprising the transmission medium.

10. The digital visual interface link of claim 7 wherein: the test data comprises pseudo-random binary sequence data that repeats every 2 23 −1 clock cycles; and the sequence generator circuit comprises: twenty three clocked flip flops coupled in series including a first flip flop, twenty one middle flip flops, and a last flip flop, each flip flop comprising a D-type flip flop comprising a D input and a Q output, the Q output of the first flip flop being coupled to the D input of one of the middle flip flops, the D input of the last flip flop being coupled to the Q output of one of the middle flip flops, and the D input of each middle flip flop being coupled to the Q output of one of the flip flops in the sequence generator circuit; an exclusive-NOR gate having a first input coupled to the Q output of the last flip flop, a second input coupled to the Q output of a middle flip flop that is separated from the last flip flop by four of the middle flip flops, and an output coupled to the D input of the first flip flop to provide feedback for the sequence generator circuit; and an inverter having an input coupled to the Q output of the last flip flop and an output to generate the pseudo-random binary sequence data.

11. A information-handling system of the type including the digital visual interface link of claim 7 , and further comprising: a processor including the encoder, the serializer, the sequence generator circuit, and the multiplexer; a display unit including the receiver; a memory device; an input/output subsystem; and a bus coupled to the processor, the memory device, the display unit, and the input/output subsystem, the bus including the transmission medium.

12. An information-handling system comprising: a digital visual interface link comprising a transmitter, a receiver, and a transmission medium coupled between the transmitter and the receiver to transmit digital visual information; a processor including the transmitter; a display unit including the receiver; an input/output subsystem; a memory device; a bus coupled to the processor, the memory device, the display unit, and the input/output subsystem; and wherein: the transmitter comprises: a transition minimized differential signaling encoder coupled to receive digital data from a plurality of parallel lines to encode the digital data into encoded digital data; a serializer coupled to receive the encoded digital data from the encoder through a plurality of parallel lines to serialize the encoded digital data into encoded and serial digital data; a pseudo-random binary sequence generator circuit to generate test data; a multiplexer coupled to receive the encoded and serial digital data from a first line coupled to the serializer and the test data from a second line coupled to the sequence generator circuit, the multiplexer to transmit the encoded and serial digital data to the transmission medium in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the transmission medium; and wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip; and the receiver comprises: a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines; and a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data.

13. The information-handling system of claim 12 wherein: the digital data comprises digital visual information comprising red data to generate red color in a visual image, green data to generate green color in the visual image, and blue data to generate blue color in the visual image; the transmission medium comprises one or more conductive wires such as copper cables, or one or more optical fibers, or one or more fiber optic cables; and the receiver further comprises external terminals to be coupled to a bit error rate test set device to couple the test data transmitted over the transmission medium in the test mode of operation to the bit error rate test set device to analyze the test data and determine if there was any corruption of the test data.

14. The information-handling system of claim 12 , further comprising a buffer circuit coupled between the multiplexer and the transmission medium to convert the encoded and serial digital data in the normal mode of operation or the test data in the test mode of operation into a differential signal to be transmitted over a pair of differential lines comprising the transmission medium.

15. The information-handling system of claim 12 wherein: the test data comprises pseudo-random binary sequence data that repeats every 2 23 −1 clock cycles; and the sequence generator circuit comprises: twenty three clocked flip flops coupled in series including a first flip flop, twenty one middle flip flops, and a last flip flop, each flip flop comprising a D-type flip flop comprising a D input and a Q output, the Q output of the first flip flop being coupled to the D input of one of the middle flip flops, the D input of the last flip flop being coupled to the Q output of one of the middle flip flops, and the D input of each middle flip flop being coupled to the Q output of one of the flip flops in the sequence generator circuit; an exclusive-NOR gate having a first input coupled to the Q output of the last flip flop, a second input coupled to the Q output of a middle flip flop that is separated from the last flip flop by four of the middle flip flops, and an output coupled to the D input of the first flip flop to provide feedback for the sequence generator circuit; and an inverter having an input coupled to the Q output of the last flip flop and an output to generate the pseudo-random binary sequence data.

16. A method of transmitting data through a link comprising: encoding digital data into encoded digital data in a transition minimized differential signaling encoder; serializing the encoded digital data into encoded and serial digital data in a serializer; generating test data in a pseudo-random binary sequence generator circuit; and transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation selected by a test signal coupled to the multiplexer, the multiplexer being fabricated with the encoder, the serializer, and the sequence generator circuit in a single integrated circuit chip.

17. The method of claim 16 wherein encoding digital data further comprises encoding digital data comprising red data to generate red color in a visual image, green data to generate green color in the visual image, and blue data to generate blue color in the visual image.

18. The method of claim 16 wherein transmitting the encoded and serial digital data further comprises transmitting the encoded and serial digital data through the multiplexer to one or more conductive wires such as copper cables, or one or more optical fibers, or one or more fiber optic cables comprising the transmission medium.

19. The method of claim 16 , further comprising converting the encoded and serial digital data or the test data transmitted through the multiplexer into a differential signal in a buffer circuit to be transmitted over a pair of differential lines comprising the transmission medium.

20. The method of claim 16 wherein generating test data further comprises generating pseudo-random binary sequence data that repeats every 2 23 −1 clock cycles in a pseudo-random binary sequence generator circuit comprising twenty three clocked flip flops coupled in series.

21. The method of claim 16 , further comprising receiving and analyzing the test data transmitted over the transmission medium in the test mode of operation in a bit error rate test set device to determine if there was any corruption of the test data.

22. The method of claim 16 wherein: encoding digital data further comprises encoding the digital data in a processor including the encoder, the serializer, the sequence generator circuit, and the multiplexer, the processor being coupled to a display unit, a memory device, and an input/output subsystem through a bus in an information-handling system; and further comprising: exchanging signals comprising data or instructions over the bus between the processor, the display unit, the memory device, and the input/output subsystem; and receiving, deserializing, decoding, and displaying the encoded and serial digital data in the display unit.