Calibrating Return Time with Cross-Coupled Arbiter/Delay Circuits to Compare Clock Signals

1. An apparatus comprising input ports to receive respectively a first clock signal and a second clock signal to be resynchronized to the first clock signal; two arbiter circuits and two delay circuits, one of the arbiter circuits to receive the first clock signal and a delayed version of the second clock signal, the other arbiter circuit to receive the second clock signal and a delayed version of the first clock signal, and both arbiter circuits to determine an ordering of the two signals which it is connected to receive; and output ports to send the outputs of the arbiter circuits to a storage device.

2. The apparatus of claim 1 in which the second clock signal corresponds to data.

3. The apparatus of claim 1 in which each of the delay circuits imposes a delay that represents portions of two timing windows, one of the timing windows representing the uncertainty of timing of an edge of the first clock signal with respect to a first circuit that is timed by the first clock signal, and the other of the timing windows representing the uncertainty of timing of an edge of the second clock signal with respect to a second circuit.

4. The apparatus of claim 1 in which the storage device receives outputs of the arbiter circuits with respect to each of multiple different second clock signals.

5. An apparatus comprising: means for receiving respectively a first clock signal and a second clock signal to be resynchronized to the first clock signal; means for receiving the first clock signal and a delayed version of the second clock signal; means for receiving the second clock signal and a delayed version of the first clock signal; and output ports to send the outputs of the means for receiving to a storage device.

6. The apparatus of claim 5 in which the second clock signal corresponds to data.