Method And/Or Apparatus for Generating a Write Gated Clock Signal

1. An apparatus comprising: a first circuit configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal, wherein said gated clock signal is pulsed active while said write enable signal is active; a second circuit configured to generate said write enable signal; and a clock tree configured to distribute a plurality of said gated clock signals.

2. The apparatus according to claim 1 , wherein said gated clock signal is pulsed not more than once per write cycle.

3. The apparatus according to claim 1 , wherein said first circuit comprises a write gated clock generator circuit comprising a plurality of storage elements and a logic gate.

4. The apparatus according to claim 1 , wherein said second circuit comprises a processor.

5. The apparatus according to claim 1 , wherein a first of said plurality of gated clock signals is presented to a first storage element.

6. The apparatus according to claim 5 , wherein said first storage element is configured to receive a first enable signal.

7. The apparatus according to claim 6 , wherein a second of said plurality of gated clock signals is presented to a second storage element.

8. The apparatus according to claim 7 , wherein said second storage element is configured to receive a second enable signal.

9. The apparatus according to claim 8 , wherein said second enable signal and said second of said plurality of gated clock signals is presented to a plurality of second storage elements.

10. The apparatus according to claim 1 , wherein said gated clock signal comprises a write gated clock signal.

11. The apparatus according to claim 2 , wherein said gated clock signal reduces power consumption by not being pulsed more than once per write cycle.

12. An apparatus comprising: means for generating a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal, wherein said gated clock signal is pulsed active while said write enable signal is active; means for generating said write enable signal; and means for implementing a clock tree for presenting a plurality of said gated clock signals.

13. The apparatus according to claim 12 , wherein said gated clock signal is pulsed not more than once per write cycle.

14. A method for generating a gated clock signal comprising the steps of: (A) generating a write enable signal; (B) generating a gated clock signal in response to (i) said write enable signal and (ii) a system clock signal, wherein said gated clock signal is pulsed active while said write enable signal is active; and (C) implementing a clock tree for presenting a plurality of said gated clock signals.

15. The method according to claim 14 , wherein said gated clock signal is pulsed not more than once per write cycle.

16. The apparatus according to claim 13 , wherein said gated clock signal reduces power consumption by not being pulsed more than once per write cycle.

17. The method according to claim 15 , wherein said gated clock signal reduces power consumption by not being pulsed more than once per write cycle.

18. The apparatus according to claim 1 , wherein said gated clock signal reduces power consumption.

19. The apparatus according to claim 12 , wherein said gated clock signal reduces power consumption.