Modem for Processing Cdma Signals

1. A modem for processing a communication signal associated with a unique code-division multiple access (CDMA) code, the modem comprising: (a) an adaptive matched filter which receives the communication signal; and (b) a vector correlator which generates filter coefficients for said adaptive matched filter based on signal distortion determined by said vector correlator; said vector correlator having a processing capacity at least equal to a predetermined chip delay corresponding to said determined signal distortion, whereby said vector correlator compensates for said determined signal distortion and for multipath distortion ascertainable within its processing capacity; and said adaptive matched filter processing individual communication signals associated with said unique CDMA code using coefficients generated by said vector correlator, whereby increased signal gain is realized which is attributable in part to the compensation for said determined signal distortion.

2. The modem according to claim 1 further comprising: (c) an analog-to-digital converter, coupled to the vector correlator, which converts the communication signal to a digital signal; (d) a tracker circuit coupled to the vector correlator and the analog-to-digital converter, wherein the tracker circuit controls the converter to provide the digital signal; (e) a carrier recovery phase lock loop coupled to the vector correlator and the adaptive matched filter, the phase lock loop providing the vector correlator with a carrier-offset-phase correcting signal; (f) at least one traffic despreader, coupled to the adaptive matched filter, which outputs a despread filtered resultant signal; and (g) an automatic power control (APC) coupled to the traffic despreader, wherein the APC generates signal strength control signals for transmission to the source which has transmitted said communication signal.

3. The modem according to claim 2 wherein the digital signal includes a digital data signal and a digital pilot signal, each having the same phase distortion.

4. The modem according to claim 3 wherein the vector correlator determines, in conjunction with the carrier recovery phase lock loop, filter coefficients based on the phase distortion of the pilot signal.

5. The modem according to claim 2 further comprising: (h) a Viterbi decoder coupled to the traffic despreader and the APC; and (i) a digital-to-analog converter coupled to the Viterbi decoder, wherein the Viterbi decoder and digital-to-analog converter process the despread filtered resultant signal for output to a user.

6. The modem according to claim 1 wherein the vector correlator provides an estimate of the complex impulse response, having real and imaginary components, of a channel over which the communication channel is transmitted.

7. The modem according to claim 1 wherein the vector correlator includes a plurality of independent elements, each element for performing an open loop estimation of a sampled impulse response of said communication signal and having a locally generated pseudo random pilot code input therein to define a processing window of a predetermined number of chips.

8. The modem according to claim 7 wherein the number of chips is eleven.

9. A modem for processing an individual communication signal associated with a unique code-division multiple access (CDMA) code, the modem comprising: (a) an adaptive matched filter which receives the communication signal; and (b) a vector correlator which generates filter coefficients for said adaptive matched filter based on signal distortion determined by said vector correlator; said vector correlator having a processing capacity of at least eleven chips whereby said vector correlator compensates for known distortion and for multipath distortion ascertainable within its processing capacity; and said adaptive matched filter processing communication signals with said unique CDMA code using coefficients generated by said vector correlator.

10. The modem according to claim 9 further comprising: (c) an analog-to-digital converter, coupled to the vector correlator, which converts the communication signal to a digital signal; (d) a tracker circuit coupled to the vector correlator and the analog-to-digital converter, wherein the tracker circuit controls the converter to provide the digital signal; (e) a carrier recovery phase lock loop coupled to the vector correlator and the adaptive matched filter, the phase lock loop providing the vector correlator with a carrier-offset-phase correcting signal; (f) at least one traffic despreader, coupled to the adaptive matched filter, which outputs a despread filtered resultant signal; and (g) an automatic power control (APC) coupled to the traffic despreader, wherein the APC generates signal strength control signals for transmission to the source which has transmitted said communication signal.

11. The modem according to claim 10 wherein the digital signal includes a digital data signal and a digital pilot signal, each having the same phase distortion.

12. The modem according to claim 11 wherein the vector correlator determines, in conjunction with the carrier recovery phase lock loop, filter coefficients based on the phase distortion of the pilot signal.

13. The modem according to claim 10 further comprising: (h) a Viterbi decoder coupled to the traffic despreader and the APC; and (i) a digital-to-analog converter coupled to the Viterbi decoder, wherein the Viterbi decoder and digital-to-analog converter process the despread filtered resultant signal for output to a user.

14. The modem according to claim 9 wherein the vector correlator provides an estimate of the complex impulse response, having real and imaginary components, of a channel over which the communication channel is transmitted.

15. The modem according to claim 9 wherein the vector correlator includes a plurality of independent elements, each element for performing an open loop estimation of a sampled impulse response of said communication signal and having a locally generated pseudo random pilot code input therein to define a processing window of eleven chips.