Method and System for Obtaining a Feasible Integer Solution from a Half-Integer Solution in Hierarchical Circuit Layout Optimization

1. A method of creating a circuit layout based on a plurality of constraints and at least one objective, comprising the steps of: (a) constructing a Boolean satisfiability problem containing a plurality of constraints and at least one objective; (b) determining if said at least one objective renders said Boolean satisfiability problem unsatisfiable; (c) if said at least one objective renders said Boolean satisfiability problem unsatisfiable, removing said at least one objective so as to form a reduced Boolean satisfiability problem, wherein said reduced Boolean satisfiability problem comprises a plurality of variables and the method further comprises: the step of rounding non-integer results of an linear program (LP) based on a truth assignment to said variables of said reduced Boolean satisfiability problem; and (d) creating a circuit layout as a function of said reduced Boolean satisfiability problem.

2. A method according to claim 1 , wherein said rounding step includes rounding up each of said non-integer results corresponding to a TRUE one of said variables and rounding down each of said non-integer results corresponding to a FALSE one of said variables.

3. A method according to claim 1 , wherein step (b) comprises the step of constructing a directed graph.

4. A method according to claim 3 , wherein step (b) further comprises determining the strongly connected components of said directed graph.

5. A method according to claim 4 , wherein said Boolean satisfiability problem comprises a plurality of variables and step (b) further comprises, after determining strongly connected components of said directed graph, performing a truth assignment to said plurality of variables.

6. A method according to claim 1 , further comprising, prior to step (a), the step of solving an linear problem LP comprising said plurality of constraints and said at least one objective so as to obtain a rational solution.

7. A method according to claim 1 , wherein said Boolean satisfiability problem comprises a plurality of constraints and a plurality of objectives and step (c) includes removing a subset of said plurality of objectives.

8. A computer readable medium containing computer instructions for creating a circuit layout based on a plurality of constraints and at least one objective, said computer instructions comprising: (a) a first set of instructions for constructing a Boolean satisfiability problem containing a plurality of constraints and a plurality of objectives; (b) a second set of instructions for determining if at least one of said plurality of objectives renders said Boolean satisfiability problem unsatisfiable; (c) a third set of instructions for removing at least one of said plurality of objectives so as to form a reduced Boolean satisfiability problem, wherein said reduced Boolean satisfiability problem comprises a plurality of variables and the computer instructions further include a fifth set of instructions for rounding non-integer results of an linear program (LP) based on a truth assignment to said variables of said reduced Boolean satisfiability problem; and (d) a fourth set of instructions for creating a circuit layout as a function of said reduced Boolean satisfiability problem.

9. A computer readable medium according to claim 8 , wherein said fifth set of instructions includes instructions for rounding up each of said non-integer results corresponding to a TRUE one of said variables and rounding down each of said non-integer results corresponding to a FALSE one of said variables.

10. A computer readable medium according to claim 8 , wherein said second set of instructions includes instructions for constructing a directed graph.

11. A computer readable medium according to claim 10 , wherein said second set of instructions further includes instructions for determining the strongly connected components of said directed graph.

12. A system, comprising: (a) at least one computer processor; and (b) at least one memory device operatively coupled to said at least one computer processor, said at least one memory device containing computer instructions for creating a circuit layout based on a plurality of constraints and a plurality of objectives, said computer instructions comprising: (i) a first set of instructions for constructing a Boolean satisfiability problem containing said plurality of constraints and said plurality of objectives; (ii) a second set of instructions for determining if any of said plurality of objectives renders said Boolean satisfiability problem unsatisfiable; (iii) a third set of instructions for removing said at least one of said plurality of objectives so as to form a reduced Boolean satisfiability problem, wherein said reduced Boolean satisfiability problem comprises a plurality of variables and the computer instructions further include a fifth set of instructions for rounding non-integer results of an linear program (LP) based on a truth assignment to said variables of said reduced Boolean satisfiability problem; and (iv) a fourth set of instructions for creating a circuit layout as a function of said reduced Boolean satisfiability problem.

13. A system according to claim 12 , wherein said fifth set of instructions includes instructions for rounding up each of said non-integer results corresponding to a TRUE one of said variables and rounding down each of said non-integer results corresponding to a FALSE one of said variables.

14. A system according to claim 12 , wherein said second set of instructions includes instructions for constructing a directed graph.

15. A system according to claim 14 , wherein said second set of instructions further includes instructions for determining strongly connected components of said directed graph.

16. A system according to claim 12 , further comprising at least one fabrication tool operatively connected to said at least one computer processor.

17. A system according to claim 12 , further comprising a sixth set of instructions for solving an linear problem LP comprising said plurality of constraints and said plurality of objectives so as to obtain a rational solution.