Gold Code Generator Design

1. A gold code generator comprising: multiple pairs of linear feedback shift registers to simultaneously produce more than one state bit and more than one output bit for each pair of linear feedback shift registers, wherein seed values for a first pair of linear feedback shift registers are different from seed values for other pairs of linear feedback shift registers.

2. The gold code generator of claim 1 , wherein the seed values for the other pairs of linear feedback shift registers are calculated from the seed values for the first pair of linear feedback shift registers.

3. The gold code generator of claim 1 , wherein the seed values for the other pairs of linear feedback shift registers are delayed values of the seed values for the first pair of linear feedback shift registers.

4. The gold code generator of claim 1 , wherein a feedback for each pair of linear feedback registers is implemented using lookup tables.

5. A method comprising: implementing a configuration of a gold code generator, the gold code generator including multiple pairs of linear feedback shift registers to simultaneously produce more than one state bit and more than one output bit for each pair of linear feedback shift registers, wherein seed values for a first pair of linear feedback shift registers are different from seed values for other pairs of linear feedback shift registers.

6. The method according to claim 5 , wherein the implementing of the gold code generator configuration occurs in a reconfigurable chip.

7. A method according to claim 6 , wherein at least a portion of the more than one output bit from the gold code generator configuration is used for configuring a configurable element of the reconfigurable chip.

8. A method according to claim 7 , wherein the more than one output bit from the gold code generator configuration is calculated by logic on the reconfigurable chip.

9. A system comprising: a gold code generator, wherein the gold code generator comprises multiple pairs of linear feedback shift registers to simultaneously produce more than one state bit and more than one output bit for each linear feedback shift registers; a reconfigurable chip that includes logic to implement a configuration of the gold code generator; and a communication element, coupled with the reconfigurable chip, to receive output from the reconfigurable chip to enable wireless communication.

10. A system according to claim 9 , wherein the gold code generator configuration is loaded into a background plane of the reconfigurable chip while the reconfigurable chip is operating on another configuration in a foreground plane, wherein once the gold code generator configuration is loaded into the background plane, the gold code generator configuration can be activated to produce an output used to configure a configurable element of the reconfigurable chip.

11. A system according to claim 10 , wherein the logic activates the gold code generator configuration to calculate the more than one state and output bits of the gold code generator.

12. A system according to claim 9 , wherein the communication element is a transmitter for spread spectrum transmission.

13. A system according to claim 9 , wherein the communication element is a receiver for spread spectrum reception.