Memory System Having Two-Way Ring Topology and Memory Device and Memory Module for Ring-Topology Memory System

1. A memory system, comprising: a signal path shared by command and address (CA) signals and data signals; a memory controller transmitting the CA signals without the data signals at a first end of the signal path in a first direction along the signal path and transmitting the data signals without the CA signals at a second end of the signal path in a direction opposite to the first direction along the signal path; and at least one memory module, the memory modules and the memory controller being connected by the signal path in a closed-loop configuration.

2. The memory system of claim 1 , wherein the signal path comprises a plurality of signal lines, wherein the quantity of signal lines is M if M is greater than N and the quantity of signal lines is N if N is greater than M, wherein M is the number of CA signals and N is the number of data signals.

3. The memory system of claim 1 , wherein the CA signals are output by a first port of the memory controller on the signal path, and the data signals are transmitted by a second port of the memory controller on the signal path.

4. The memory system of claim 1 , wherein one of the CA signals and data signals is output by a first port of the memory controller at the first end of the signal path, and the other of the data signals and CA signals is output by a second port of the memory controller at the second end of the signal path.

5. The memory system of claim 1 , wherein the memory modules comprise first and second ports for receiving the CA signals and data signals.

6. The memory system of claim 5 , wherein the ports are multi-functional ports which can output the CA signals and receive the data signals or can output tile data signals and receive the CA signals.

7. The memory system of claim 6 , wherein a first port of a memory module is an input port and an output port for the data signals and the CA signals, respectively.

8. The memory system of claim 7 , wherein a second port of a memory module is an input port and an output port for the CA signals and the data signals, respectively.

9. The memory system of claim 5 , wherein each memory module comprises a destination circuit for determining whether a received signal is intended to be processed by a memory device on the memory module.

10. The memory system of claim 9 , wherein each memory module comprises an output buffer for outputting a received signal to the signal path if it is determined that die received signal is not intended to be processed by a memory device on the memory module.

11. The memory system of claim 1 , wherein each memory module comprises a synchronization circuit for compensating for a delay of a received signal on the signal path.

12. The memory system of claim 1 , wherein each memory module comprises a destination circuit for determining whether a received signal is a CA signal or a data signal.

13. The memory system of claim 12 , wherein the destination circuit generates a signal mode signal indicative of whether the received signal is a data signal or a CA signal.

14. The memory system of claim 1 , wherein each memory module comprises a router circuit for routing a received signal identified as a data signal to a memory device of the memory module on a data signal line and for routing a received signal identified as a CA signal to the memory device on a CA signal line.

15. A memory system, comprising: a signal path shared by command and address (CA) signals and data signals; a memory controller executing: one of transmitting the CA signals without the data signals in a first direction and transmitting the data signals without the CA signals in the first direction at a first end of the signal path, and the other of transmitting the CA signals without the data signals in a second direction opposite to the first direction and transmitting the data signals without the CA signals in the second direction opposite to the first direction at a second end of the signal path; and a memory module having at least one memory device, the memory module and the memory controller being connected by the signal path in a closed-loop configuration.

16. The memory system of claim 9 , wherein each memory module sends the received signal to the memory device if it is determined that the received signal is intended to be processed by the memory device on the memory module.

17. The memory system of claim 9 , wherein each memory module sends the received signal to the memory device and outputs the data signal of the memory device to the second port if it is determined that the CA signal received to the first port is intended to be processed by the memory device on the memory module.