Computer Instructions for Having Extended Signed Displacement Fields for Finding Instruction Operands

1. A method for executing a machine instruction in a central processing unit, the method comprising the steps of: fetching a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising an opcode field, an operand base address field and a displacement field containing a displacement value, the displacement field comprising any one of: 1) an unsigned displacement field consisting of only an unsigned portion of a given magnitude, the unsigned portion comprising a most significant bit at one end and a least significant bit at the other end or 2) a signed displacement field consisting of a signed portion contiguous with said unsigned portion, wherein said least significant bit of said unsigned portion is contiguous with said signed portion; obtaining an operand base address from a location specified by the operand base address field; determining if the displacement field is an unsigned displacement field or a signed displacement field; if the displacement field is an unsigned displacement field, arithmetically adding the magnitude of the unsigned portion to the operand base address to determine an address of an operand; if the displacement field is a signed displacement field, concatenating the signed portion with the most significant bit of said unsigned portion to form a signed displacement value wherein the signed portion is a high order portion of said signed displacement value and said unsigned portion is a low order portion of said signed displacement value and algebraically summing the signed displacement value and the operand base address to determine an address of an operand; and performing a function defined by the opcode field, wherein the function uses the operand at the determined address.

2. The method according to claim 1 , wherein said step of obtaining an operand base address comprises the step of retrieving from the operand base address field a base address field value, the base address field value comprising the location in a storage of the operand base address, said method comprising the further steps of: determining a function to be executed based on the opcode field value, and wherein said step of performing a function defined by the opcode field comprises the steps of: determining if the operand is a source operand or a result operand; (a) if the operand is determined to be a source operand: (1) fetching the operand at the determined address; (2) executing the determined function to be executed on the fetched operand to determine a first result value of a first result operand; and (3) storing the first result value of the first result operand of the executing; and (b) if the operand is determined to be a result operand; (1) fetching a source operand; (2) executing the determined function to be executed on the fetched source operand to determine a second result value of the operand; and (3) storing at the determined address, the second result value of the operand of the executing step.

3. The method according to claim 1 , wherein the displacement field consists of any one of 12 bits or 20 bits, wherein the signed portion consists of an 8 bit most significant portion and the unsigned portion consists of a 12 bit least significant portion.

4. The method according to claim 1 , wherein the machine instruction comprises bit j of the signed portion contiguous with the unsigned portion wherein bit j is a sign bit indicating that the displacement value is any one of a positive displacement value or a negative displacement value.

5. The method according to claim 1 , wherein the unsigned portion of the machine instruction occupies the same bit positions as an unsigned displacement field in machine instructions of the same architecture.

6. The method according to claim 1 , wherein the machine instruction consists of 48 bits, wherein the opcode consists of bits 0 – 7 and 40 – 47 , a first operand locating field consists of bits 8 – 11 , a second operand locating field consists of bits 12 – 15 , the base address field comprises bits 16 – 19 , the unsigned portion of the displacement field comprises bits 20 – 31 , and the signed portion of the signed displacement field consists of bits 32 – 39 .

7. The method according to claim 1 , wherein the machine instruction defined for the computer architecture is fetched and executed by a central processing unit of an alternate computer architecture, the method comprising the further steps of: interpreting the machine instruction to identify a predetermined software subroutine for emulating the operation of the machine instruction, the predetermined software subroutine comprising a plurality of instructions; and executing the predetermined software subroutine to perform steps of the method for executing the machine instruction.

8. The method according to claim 1 , wherein the computer architecture is the IBM z/Architecture, wherein the machine instruction format consists of any one of RXY, RSY or SIY.

9. The method according to claim 1 , wherein the machine instruction further comprises any one of a third operand field, a mask field or an index field.

10. The method according to claim 1 , wherein the determined function to be executed further employs a value consisting of any one of an immediate field value of an immediate field of the machine instruction, a mask field value of the machine instruction or a general purpose register value obtained from a general purpose register location determined by a value of a register field of the machine instruction.

11. A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising: a storage memory readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: fetching a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising an opcode field, an operand base address field and a displacement field containing a displacement value, the displacement field comprising any one of: 1) an unsigned displacement field consisting of only an unsigned portion of a given magnitude, the unsigned portion comprising a most significant bit at one end and a least significant bit at the other end or 1a signed displacement field consisting of a signed portion contiguous with said unsigned portion, wherein said least significant bit of said unsigned portion is contiguous with said signed portion; obtaining an operand base address from a location specified by the operand base address field; determining if the displacement field is an unsigned displacement field or a signed displacement field; if the displacement field is an unsigned displacement field, arithmetically adding the magnitude of the unsigned portion to the operand base address to determine an address of an operand; if the displacement field is a signed displacement field, concatenating the signed portion with the most significant bit of said unsigned portion to form a signed displacement value wherein the signed portion is a high order portion of said signed displacement value and said unsigned portion is a low order portion of said signed displacement value and algebraically summing the signed displacement value and the operand base address to determine an address of an operand; and performing a function defined by the opcode field, wherein the function uses the operand at the determined address.

12. The computer program product according to claim 11 , wherein said step of obtaining an operand base address comprises the step of retrieving from the operand base address field a base address field value, the base address field value comprising the location in a storage of the operand base address, said method further comprising: determining a function to be executed based on the opcode field value, and wherein said step of performing a function defined by the opcode field comprises the steps of: determining if the operand is a source operand or a result operand: (a) if the operand is determined to be a source operand; (1) fetching the operand at the determined address; (2) executing the determined function to be executed on the fetched operand to determine a first result value of a first result operand; and (3) storing the first result value of the first result operand of the executing step; and (b) if the operand is determined to be a result operand; (1) fetching a source operand; (2) executing the determined function to be executed on the fetched source operand to determine a second result value of the operand; and (3) storing at the determined address, the second result value of the operand of the executing step.

13. The computer program product according to claim 11 , wherein the unsigned portion consists of bits l through m, wherein further the signed portion consists of bits i through k of the signed displacement machine instruction, wherein bit k is a bit position of a least significant bit of the signed portion and wherein bit m is a bit position of a least significant bit of the unsigned portion.

14. The computer program product according to claim 11 , wherein the machine instruction comprises bit j of the signed portion contiguous with the unsigned portion wherein bit j is a sign bit indicating that the displacement value is any one of a positive displacement value or a negative displacement value.

15. The computer program product according to claim 11 , wherein the unsigned portion of the machine instruction occupies the same bit positions as an unsigned displacement field in machine instructions of the same architecture.

16. The computer program product according to claim 11 , wherein the machine instruction consists of 48 bits, wherein the opcode consists of bits 0 – 7 and 40 – 47 , a first operand locating field consists of bits 8 – 11 , a second operand locating field consists of bits 12 – 15 , the base address field comprises bits 16 – 19 , the unsigned portion of the displacement field comprises bits 20 – 31 , and the signed portion of the signed displacement field consists of bits 32 – 39 .

17. The computer program product according to claim 11 , wherein the machine instruction defined for the computer architecture is fetched and executed by a central processing unit of an alternate computer architecture, the method comprising the further steps of: interpreting the machine instruction to identify a predetermined software subroutine for emulating the operation of the machine instruction, the predetermined software subroutine comprising a plurality of instructions; and executing the predetermined software subroutine to perform steps of the method for executing the machine instruction.

18. The computer program product according to claim 11 , wherein the computer architecture is the IBM z/Architecture, wherein the machine instruction format consists of any one of RXY, RSY or SIY.

19. The computer program product according to claim 11 , wherein the machine instruction further comprises any one of a third operand field, a mask field or an index field.

20. The computer program product according to claim 11 , wherein the determined function to be executed further employs a value consisting of any one of an immediate field value of an immediate field of the machine instruction, a mask field value of the machine instruction or a general purpose register value obtained from a general purpose register location determined by a value of a register field of the machine instruction.

21. A system for executing a machine instruction in a central processing unit, the system comprising: a memory; a computer system in communication with the memory, the computer system comprising an instruction fetching unit for fetching instructions from memory and one or more execution units for executing fetched instructions; wherein the computer system includes instructions to execute a method comprising: fetching a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising an opcode field, an operand base address field and a displacement field containing a displacement value, the displacement field comprising any one of: 1) an unsigned displacement field consisting of only an unsigned portion of a given magnitude, the unsigned portion comprising a most significant bit at one end and a least significant bit at the other end or 2) a signed displacement field consisting of a signed portion contiguous with said unsigned portion, wherein said least significant bit of said unsigned portion is contiguous with said signed portion; obtaining an operand base address from a location specified by the operand base address field; determining if the displacement field is an unsigned displacement field or a signed displacement field; if the displacement field is an unsigned displacement field, arithmetically adding the magnitude of the unsigned portion to the operand base address to determine an address of an operand; if the displacement field is a signed displacement field, concatenating the signed portion with the most significant bit of said unsigned portion to form a signed displacement value and algebraically summing the signed displacement value wherein the signed portion is a high order portion of said signed displacement value and said unsigned portion is a low order portion of said signed displacement value and algebraically summing the signed displacement value and the operand base address to determine an address of an operand; and performing a function defined by the opcode field, wherein the function uses the operand at the determined address.

22. The system according to claim 21 , wherein said step of obtaining an operand base address comprises the step of retrieving from the operand base address field a base address field value, the base address field value comprising the location in a storage of the operand base address, said method further comprising: determining a function to be executed based on the opcode field value, and wherein said step of performing a function defined by the opcode field comprises the steps of: determining if the operand is a source operand or a result operand; (a) if the operand is determined to be a source operand: (1) fetching the operand at the determined address; (2) executing the determined function to be executed on the fetched operand to determine a first result value of a first result operand; and (3) storing the first result value of the first result operand of the executing step; and (b) if the operand is determined to be a result operand: (1) fetching a source operand; (2) executing the determined function to be executed on the fetched source operand to determine a second result value of the operand; and (3) storing at the determined address, the second result value of the operand of the executing step.

23. The system according to claim 21 , wherein the displacement field consists of any one of 12 bits or 20 bits, wherein the signed portion consists of an 8 bit most significant portion and the unsigned portion consists of a 12 bit least significant portion.

24. The system according to claim 21 , wherein the machine instruction comprises bit j of the signed portion contiguous with the unsigned portion wherein bit j is a sign bit indicating that the displacement value is any one of a positive displacement value or a negative displacement value.

25. The system according to claim 21 , wherein the unsigned portion of the machine instruction occupies the same bit positions as an unsigned displacement field in machine instructions of the same architecture.

26. The system according to claim 21 , wherein the machine instruction consists of 48 bits, wherein the opcode consists of bits 0 – 7 and 40 – 47 , a first operand locating field consists of bits 8 – 11 , a second operand locating field consists of bits 12 – 15 , the base address field comprises bits 16 – 19 , the unsigned portion of the displacement field comprises bits 20 – 31 , and the signed portion of the signed displacement field consists of bits 32 – 39 .

27. The system according to claim 21 , wherein the machine instruction defined for the computer architecture is fetched and executed by a central processing unit of an alternate computer architecture, the method comprising the further steps of: interpreting the machine instruction to identify a predetermined software subroutine for emulating the operation of the machine instruction, the predetermined software subroutine comprising a plurality of instructions; and executing the predetermined software subroutine to perform steps of the method for executing the signed displacement machine instruction.

28. The system according to claim 21 , wherein the computer architecture is the IBM z/Architecture, wherein the machine instruction format consists of any one of RXY, RSY or SIY.

29. The system according to claim 21 , wherein the machine instruction further comprises any one of a third operand field, a mask field or an index field.

30. The system according to claim 21 , wherein the determined function to be executed further employs a value consisting of any one of an immediate field value of an immediate field of the machine instruction, a mask field value of the machine instruction or a general purpose register value obtained from a general purpose register location determined by a value of a register field of the machine instruction.

31. The system according to claim 1 , wherein the determining if the displacement field is an unsigned displacement field or a signed displacement field step comprises decoding the opcode field of the machine instruction.

32. The program product according to claim 11 , wherein the determining if the displacement field is an unsigned displacement field or a signed displacement field step comprises decoding the opcode field of the machine instruction.

33. The system according to claim 21 , wherein the determining if the displacement field is an unsigned displacement field or a signed displacement field step comprises decoding the opcode field of the machine instruction.