Legal claims defining the scope of protection, as filed with the USPTO.
1. A shift register comprising: a plurality of stages including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock and a first control signal, the first clock being prevented from being outputted from each of the odd numbered stages in response to the first control signal, the even numbered stages respectively receiving a second clock and a second control signal, the second clock being prevented from being outputted from each of the even numbered stages in response to the second control signal, the second clock having a first phase 180° different from a second phase of the first clock, the stages respectively delaying the first clock or the second clock by a first period to sequentially output the first clock end the second clock as a scan line driving signal; a dummy stage for generating a dummy output signal, the scan line driving signal of a last stage falling below a first predetermined voltage level in response to the dummy output signal of the dummy stage, the dummy output signal being delayed by a second period and falling below a second predetermined voltage level in response to the dummy output signal.
2. The shift register of claim 1 , wherein each of the stages comprises: a pull-up part for providing an output terminal of each of the stages with the first clock or the second clock with; a pull-down part for providing the output terminal of each of the stage with a first power voltage; a pull-up driver part for turning on the pull-up part in response to the scan line driving signal of a previous stage and turning off the pull-up part in response to the first control signal or the second control signal; and a pull-down driver part for turning off the pull-up part in response to the scan line driving signal of the previous stage and turning on the pull-up part in response to the first control signal or the second control signal.
3. The shift register of claim 1 , wherein the dummy stage comprises: a dummy pull-up part for providing a dummy output terminal with the first clock or the second clock; a dummy pull-down part for providing the dummy output terminal with the first power voltage; a dummy pull-up driver part for turning on the dummy pull-up part in response to the scan line driving signal of the last stage and turning off the dummy pull-up part rnreuponse to the first clock or the second clock that is applied to the dummy pull-up driver part through the dummy pull-up part: and a dummy pull-down driver part for turning off the dummy pull-down part in response to the scan line driving signal of the last stage and turning on the dummy pull-down part in response to the first control signal or the second control signal.
4. The shift register of claim 3 , wherein the dummy pull-up driver part comprises: a capacitor coupled between a first input node of the dummy pull-up part and the dummy output terminal; a first transistor, a first drain of the first transistor receiving the first power voltage, a first gate of the first transistor receiving the scan line driving signal of the previous stage, and a first source of the first transistor coupled to the first input node of the dummy pull-up part; a second transistor, a second drain of the second transistor coupled to the first input node of the dummy pull-up part, a second gate of the second transistor coupled to a second input node of the dummy pull-down part, and a second source of the second transistor receiving the first power voltage; and a third transistor, a third drain of the third transistor coupled to the first input node of the dummy pull-up part, a third gate of the third transistor coupled to an output terminal of the dummy pull-up part, and a third source of the third transistor receiving the first power voltage.
5. A shift register comprising: a plurality of stages including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock and a first control signal, the first clock being prevented from being outputted from each of the odd numbered stages in response to the first control signal, the even numbered stages respectively receiving a second clock and a second control signal, the second clock being prevented from being outputted from each of the even numbered stages in response to the second control signal, the second clock having a first phase 180° different from a second phase of the first clock, the stages respectively delaying the first clock or the second clock by a first period to sequentially output the first clock and the second clock as a scan line driving signal; a dummy stage, coupled to a last stage, for generating a dummy output signal, the scan line driving signal of the last stage falling below a first predetermined voltage level in response to the dummy output signal of the dummy stage, the dummy output signal being delayed by a second period and falling below a second predetermined voltage level in response to a control signal of the last stage.
6. The shift register of claim 5 , wherein each of the stages comprises: a pull-up part for providing a first output terminal of each of the stages with the first clock or the second clock; a pull-down part for providing the first output terminal of each of the stages with a first power voltage; a pull-up driver part for turning on the pull-up part in response to the scan line driving signal of a previous stage and turning off the pull-up part in response to the first control signal or the second control signal; and a pull-down driver part for turning off the pull-up part in response to the scan line driving signal of the previous stage and turning on the pull-up part in response to the first control signal or the second control signal.
7. The shift register of claim 5 , wherein the dummy stage comprises: a dummy pull-up part for providing a dummy output terminal with the first clock or the second clock; a dummy pull-down part for providing the dummy output terminal with a first power voltage; a dummy pull-up driver part for turning on the dummy pull-up part in response to the scan line driving signal of the last stage and turning off the dummy pull-up part when the pull-down driver part of the last stage is turned off; and a dummy pull-down driver part for turning off the dummy pull-down part in response to the scan line driving signal of the last stage and turning on the dummy pull-down part in response to the first control signal or the second control signal.
8. The shift register of claim 7 , wherein the dummy pull-up driver part comprises: a capacitor coupled between a first input node of the dummy pull-up part and the dummy output terminal, a first transistor, a first drain of the first transistor receiving the first power voltage, a first gate of the first transistor receiving the scan line driving signal of the previous stage, and a first source of the first transistor coupled to the first input node of the dummy pull-up part; a second transistor, a second drain of the second transistor coupled to the first input node of the dummy pull-up part, a second gate of the second transistor coupled to a second input node of the dummy pull-down part, and a second source of the second translator receiving the first power voltage; and a third transistor, a third drain of the third transistor coupled to the first input node of the dummy pull-up part, a third gate of the third transistor coupled to a second output terminal of the dummy pull-down driver part of the last stage, and a third source of the third transistor receiving the first power voltage.
9. A shift register including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock, the even numbered stages respectively receiving a second clock having a first phase 180° different from a second phase of the first clock, the shift register comprising: a first stage performing a forward shift from the first stage to a last stage when a first selection signal has a first voltage level and performing a backward shift from the last stage to the first stage when a second selection signal has the first voltage level; a Nth stage performing the forward shift from the first stage to the last stage when the first selection signal has the first voltage level and performing the backward shift from the last stage to the first stage when the second selection signal has the first voltage level, N being an integer greater than or equal to 2; a last stage performing the forward shift from the first stage to the last stage when the first selection signal has the first voltage level and performing the backward shift from the last stage to the first stage when the second selection signal has the first voltage level; a first dummy stage for inactivating the last stage during the forward shift; and a second dummy stage for inactivating the first stage during the backward shift.
10. The shift register of claim 9 , wherein the first selection signal has a first phase 180° different from a second phase of the second selection signal.
11. The shift register of claim 9 , wherein the first and second selection signals have a first electric potential higher than a second electric potential of the first and second clocks.
12. The shift register of claim 9 , wherein a shift direction of the stages is changed by exchanging the first clock and the second clock in correspondence with the first and second selection signal.
13. The shift register of claim 9 , wherein each of the stages includes a plurality of transistors, each of the transistors being a-Si NMOS transistor.
14. The shift register of claim 9 , wherein the first and second selection signals have a first electric potential higher than a second electric potential of the first and second clocks.
15. The shift register of claim 9 , wherein a shift direction of the stages is changed by exchanging the first clock and the second clock in correspondence with the first and second selection signal.
16. The shift register of claim 9 , wherein each of the stages includes a plurality of transistors, each of the transistors being a-Si NMOS transistor.
17. A shift register including odd numbered stages and even numbered stages, the odd numbered stages respectively receiving a first clock, the even numbered stages respectively receiving a second clock having a first phase 180° different from a second phase of the first clock, the stages of the shifter register being sequentially shifted in synchronization with the first and second clock signals in a forward direction and in a backward direction, the shift register comprising: a first stage receiving a scan start signal to generate a first scan line driving signal when a first selection signal has a first voltage level and lowering a second voltage level of the first scan line driving signal in response to a second scan line driving signal generated from a second stage, the first stage generating the first scan line driving signal in response to the second scan line driving signal when a second selection signal has the first voltage level and lowering the second voltage level of the first scan line driving signal in response to a second dummy output signal; a Nth stage generating a Nth scan line driving signal in response to a (N−1)th scan line driving signal outputted from a (N−1)th stage when the first selection signal has the first voltage level and lowering a third voltage level of the Nth scan line driving signal in response to an (N+1)th scan line driving signal outputted from an (N+1)th stage, the Nth stage generating the Nth scan line driving signal in response to the (N+1)th scan line driving signal when the second selection signal has the first voltage level and lowering the third voltage level of the Nth scan line driving signal in response to the (N−1)th scan line driving signal, N being an integer greater than 2; a Mth stage generating a Mth scan line driving signal in response to a (M−1)th scan line driving signal outputted from a (M−1)th stage when the first selection signal has the first voltage level and lowering a fourth voltage level of the Mth scan line driving signal in response to a first dummy output signal, the Mth stage generating the Mth scan line driving signal in response to the scan start signal when the second selection signal has the first voltage level and lowering the fourth voltage level of the Mth scan line driving signal in response to the (M−1)th scan line driving signal, M being the integer greater than N; a first dummy stage receiving the first clock signal and to Mth scan line driving signal to generate the first dummy output signal, and the first dummy stage lowering a fifth voltage level of the first dummy output signal in response to the scan start signal; and a second dummy stage receiving the second clock signal and the first scan line driving signal to generate the second dummy output signal, and the second dummy stage lowering a sixth voltage level of the second dummy output signal in response to the scan start signal.
18. The shift register of claim 17 , wherein the first stage including: a pull-up transistor for providing an output terminal of the first stage with the first scan line driving signal; a pull-down transistor for providing the output terminal of each of the stages with a first power voltage; a first pull-up driver transistor turning on the pull-up transistor in response to the scan start signal inputted to the first pull-up driver transistor through a first selection transistor when the first selection signal has the first voltage level, and the first pull-up driver transistor turning off the pull-up transistor in response to the second dummy output signal inputted to the first pull-up driver transistor through a second selection transistor when the second selection signal has the first voltage level; a second pull-up driver transistor turning on the pull-up transistor in response to the second scan line driving signal when the second selection signal has the first voltage level, and the second pull-up driver transistor turning off the pull-up transistor in response to the second scan line driving signal when the first selection signal has the first voltage level; a pull-down driver part turning off the pull-down transistor in response to the scan start signal or the second dummy output signal, and the pull-down driver part turning on the pull-down transistor in response to the second scan line driving signal; and a third pull-up driver transistor being turned off when the pull-up transistor is turned on.
19. The shift register of claim 17 , wherein the Nth stage includes: a pull-up transistor for providing an output terminal of the Nth stage with the Nth scan line driving signal; a pull-dawn transistor for providing the output terminal of the Nth stage with a first power voltage; a first pull-up driver transistor turning on the pull-up transistor in response to the (N−1)th scan line driving signal when the first selection signal has the first voltage level, and the first pull-up driver transistor turning off the pull-up transistor in response to the (N−1)th scan line driving signal when the second selection signal has the first voltage level; a second pull-up driver transistor turning on the pull-up transistor in response to the (N+1)th scan line driving signal when the second selection signal has the first voltage level, and the second pull-up driver transistor turning of the pull-up transistor in response to the (N+1)th scan line driving signal when the first selection signal has to first voltage level; a pull-down driver part turning off the pull-down transistor in response to the (N−1)th scan line driving signal, and the pull-down driver part turning on the pull-down transistor in response to the (N+1)th scan line driving signal; and a third pull-up driver transistor being turned off when the pull-up transistor is turned on.
20. The shift register of claim 17 , wherein the Mth stage including: a pull-up transistor for providing an output terminal of the Mth stage with the Mth scan line driving signal; a pull-down transistor for providing the output terminal of the Mth stages with a first power voltage; a first pull-up driver transistor turning on the pull-up transistor in response to the (M−1)th scan line driving signal when the first selection signal has the first voltage level, and the first pull-up driver transistor turning off the pull-up transistor in response to the (M−1)th scan line driving signal when the second selection signal has the first voltage level; a second pull-up driver transistor turning on the pull-up transistor in response to the scan start signal inputted to the second pull-up driver transistor through a third selection transistor when the second selection signal has the first voltage level, and the second pull-up driver transistor turning off the pull-up transistor in response to the first dummy output signal inputted to the second pull-up driver transistor through a fourth selection transistor when the first selection signal has the first voltage level; a pull-down driver part turning off the pull-down transistor in response to the (M−1)th scan line driving signal, and the pull-down driver part turning on the pull-down transistor in response to the first scan line driving signal and the scan start signal; and a third pull-up driver transistor being turned off when the pull-up transistor is turned on.
21. The shift register of claim 17 , wherein the first dummy stage including: a pull-up transistor for providing an output terminal of the first dummy stage with the first dummy output signal; a pull-down transistor for providing the output terminal of the first dummy stage with a first power voltage; a first pull-up driver transistor turning on the pull-up transistor in response to the Mth scan line driving signal; a second pull-up driver transistor turning off the pull-up transistor in response to the scan start signal; a pull-down driver part turning off the pull-down transistor in response to the first scan line driving signal, and the pull-down driver part turning on the pull-down transistor in response to the scan start signal; and a third pull-up driver transistor being turned off when the pull-up transistor is turned on.
22. The shift register of claim 17 , wherein the second dummy stage including: a pull-up transistor for providing an output terminal of the second dummy stage with the second dummy output signal; a pull-down transistor for providing the output terminal of the second dummy stage with a first power voltage; a first pull-up driver transistor turning on the pull-up transistor in response to the first scan line driving signal; a second pull-up driver transistor turning off the pull-up transistor in response to the scan start signal; a pull-down driver part turning off the pull-down transistor in response to the first scan line driving signal, and the pull-down driver part turning on the pull-down transistor in response to the scan start signal; and a third pull-up driver transistor being turned off when the pull-up transistor is turned on.
23. The shift register of claim 17 , wherein the first selection signal has a first phase 180° different from a second phase of the second selection signal.
Unknown
September 12, 2006
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