Iml-Stream Generated Error Insertion / Fru Isolation

1. A method for testing error detection programs dedicated for detecting hardware failures in a computer processor system, said method comprising the steps of: generating error case patterns comprising stimuli values, wherein said error case patterns are inserted into an IML-stream including a sequence of chain commands; receiving said IML-stream in an interface control operating between a user debug interface and a simulation model; converting commands comprised of said IML-stream into stimuli values for the simulation model; feeding the simulation model of the hardware with said error case patterns; running said simulation model for evaluation of model response patterns generated by the simulation model; and echoing model response patterns back to the user debug interface.

2. The method according to claim 1 , further comprising the steps of: providing an input per chain command for entering one or more stimuli values for a chain within the simulation model; and providing a status display per chain command for viewing status values of simulation model latches when the model is run.

3. The method according to claim 1 for evaluating status values of model chains including a chain comprising a plurality of latches in said model, said method further comprising the steps of: viewing simulation results on a chain using a common chain address; and sticking error values on selected ones of said latches, said sticking error values remaining unchanged until receiving an unstick command.

4. The method according to claim 1 further comprising the step of: generating an error value at a latch with a first command at a first chain address at a first location in the command stream; and reversing said error value of said latch with a second command at a second chain address at a second location in the command stream.

5. An apparatus for testing error detection programs dedicated for detecting hardware failures in a computer processor system, said apparatus comprising: a pattern generator generating error case patterns comprising stimuli values; a simulation model receiving said error case patterns of the hardware; an evaluator running said simulation model for evaluation of model response patterns generated by the simulation model; a display to view simulation results on a chain of said simulation model using a common chain address, said chain comprising a plurality of latches in said simulation model; and a module to stick error values on selected ones of said latches, said sticking error values remaining unchanged until receiving an unstick command.

6. The apparatus according to claim 5 , wherein said error case patterns are inserted into an IML-stream including a sequence of chain commands, said apparatus further comprising: a user debug interface; an interface control receiving said IML-stream in an interface control operating between said user debug interface and said simulation model; a converter converting commands comprised of said IML-stream into stimuli values for the simulation model; and an echoing model echoing response patterns back to the user debug interface.

7. The apparatus according to claim 5 , further comprising: an input in said simulation model receiving, per chain command, one or more stimuli values for a chain within the simulation model; and a status display connected to said simulation model displaying, per chain command, status values of simulation model latches when the model is run.

8. The apparatus according to claim 6 further comprising: an error value generator generating an error value at a latch with a first command at a first chain address at a first location in the command stream; and a module reversing said error value of said latch with a second command at a second chain address at a second location in the command stream.

9. A program product for use with an apparatus for testing error detection programs dedicated for detecting hardware failures in a computer processor system, said program product comprising; a computer readable medium having recorded thereon computer readable program code performing the method comprising the steps of: generating error case patterns comprising stimuli values; feeding a simulation model of the hardware with said error case patterns, wherein said feeding comprises providing an input per chain command for entering one or more stimuli values for a chain within the simulation model; running said simulation model for evaluation of model response patterns generated by the simulation model; and providing a status display per chain command for viewing status values of simulation model latches when the model is run.

10. The program product according to claim 9 , wherein said error case patterns are inserted into an IML-stream including a sequence of chain commands, said method further comprising the steps of: receiving said IML-stream in an interface control operating between a user debug interface and said simulation model; converting commands comprised of said IML-stream into stimuli values for the simulation model; and echoing model response patterns back to the user debug interface.

11. The program product according to claim 9 for evaluating status values of model chains including a chain comprising a plurality of latches in said model, said method further comprising the steps of: viewing simulation results on a chain using a common chain address; and sticking error values on selected ones of said latches, said sticking error values remaining unchanged until receiving an unstick command.

12. The program product according to claim 10 , said method further comprising the steps of: generating an error value at a latch with a first command at a first chain address at a first location in the command stream; and reversing said error value of said latch with a second command at a second chain address at a second location in the command stream.

13. A program product comprising: at least one computer usable medium having computer readable program code logic to facilitate testing of error detection programs dedicated for detecting hardware failure in a computer processor system, the computer readable program code logic performing the method comprising: generating error case patterns comprising stimuli values, wherein said error case patterns are inserted into an IML-stream including a sequence of chain commands; receiving said IML-stream in an interface control operating between a user debug interface and a simulation model; converting commands comprised of said IML-stream into stimuli values for the simulation model; feeding the simulation model of the hardware with said error case patterns; running said simulation model for evaluation of model response patterns generated by the simulation model; and echoing model response patterns back to the user debug interface.