Downstream Broadcast Pci Switch

1. A method of switching transactions on an interconnect switch, the interconnect switch having a primary port connected to a primary interconnect, a first secondary port connected to a bridge, and a plurality of end-device secondary ports, each connectable to one of a plurality of end devices, the method comprising the steps of: identifying a transaction from the primary port as a bridge transaction or a non-bridge transaction; routing the bridge transaction to the bridge through the first secondary port; and routing the non-bridge transaction to at least one of the plurality of end device secondary ports, wherein the transaction has a target address, and wherein the step of identifying a transaction as a bridge transaction or a non-bridge transaction comprising the steps of: shadowing registers of the bridge with a plurality of shadow registers in the interconnect switch; if the target address is mapped by the shadow registers, identifying the transaction as a bridge transaction; and if the target address is not mapped by the shadow registers, identifying the transaction as a non-bridge transaction.

2. The method of claim 1 , the step of shadowing registers comprising the step of: shadowing base address registers of the bridge in the switch, the base address registers of the bridge mapping addresses associated with a secondary interconnect of the bridge.

3. The method of claim 1 , the step of shadowing comprising the step of: snooping a configuration transaction that configures base address registers of the bridge; and copying base address register information obtained in the snooping step to the shadow registers.

4. The method of claim 1 , the step of routing a non-bridge transaction comprising the step of: broadcasting the non-bridge transaction to each of the plurality of end-device secondary ports.

5. The method of claim 1 , the step of routing a non-bridge transaction comprising the step of: successively routing the non-bridge transaction to each of the end-device secondary ports until the non-bridge transaction is claimed by a first end device connected to a first end-device secondary port.

6. The method of claim 5 , wherein the non-bridge transaction has a target address, further comprising the steps of: identifying an address range associated with the first end device; routing further non-bridge transactions with a target address within the address range to the first end-device secondary port; and successively routing further non-bridge transactions with a target address outside the address range to each of the other plurality of end-device secondary ports until claimed by another end device.

7. The method of claim 1 , wherein the transaction is a peer-to-peer transaction.

8. The method of claim 1 , wherein the transaction is a downstream transaction.

9. An interconnect switch, comprising: a primary port, to couple to a primary bus segment; a switch engine coupled to the primary port; a secondary-bridge port configured to couple to a secondary bus segment; and one or more secondary-end-device ports each configured to couple to an end device; wherein the switch engine comprises: circuitry to receive a transaction, the transaction having a target address; circuitry to decode the target address; circuitry to route the transaction to the secondary-bridge port if the circuitry to decode the target address decodes the target address as directed to the secondary bus segment; and circuitry to route the transaction to at least one of the one or more secondary-end-device ports if the circuitry to decode the target address decodes the target address as not directed to a bridge.

10. The interconnect switch of claim 9 , wherein the circuitry to route the transaction to at least one of the one or more secondary-end-device ports comprises circuitry to broadcast the transaction to a plurality of secondary-end-device ports.

11. The interconnect switch of claim 9 , wherein the circuitry to route the transaction to at least one of the one or more end-device ports comprises circuitry to successively route the transaction to each of the one or more secondary-end-device ports until the transaction is claimed by a claiming end device.

12. The interconnect switch of claim 11 , wherein the circuitry to route transactions to at least one of the one or more secondary-end-device ports further comprises: circuitry to store an end-device address range associated with the claiming end device; circuitry to route further transactions to the claiming end device if the target address is within the end-device address range.

13. The interconnect switch of claim 9 , wherein the transaction is a downstream transaction.

14. The interconnect switch of claim 9 , wherein the transaction is a peer-to-peer transaction.

15. The interconnect switch of claim 9 , comprising two or more secondary-end-device ports.

16. A system, comprising: a processor; a memory coupled to the processor; an interconnect bus coupled to the processor, the interconnect bus comprising: a primary bus segment coupled to the processor; a switch having a primary side with a primary port coupled to the primary bus segment and a secondary side with a plurality of secondary ports, the switch comprising a routing engine configured to selectively transmit a transaction from the primary port to at least one secondary-port of the plurality of secondary ports based on whether the transaction is targeted for a bridge, wherein the switch comprises: a shadow register; circuitry configured to snoop at least a portion of a target address of a transaction that passes through a bridge connected to one of the plurality of secondary ports; and circuitry configured to compare the snooped portion of the target address with at least a portion of a target address of an unclassified transaction to identify the unclassified transaction as a non-bridge transaction.

17. The system of claim 1 , comprising a secondary bus segment coupled to one of the plurality of secondary ports and an end device coupled to another one of the secondary ports.

18. The system of claim 1 , wherein the switch comprises circuitry configured to store the snooped portion of the target address in a shadow register.