Method and System for Port Numbering in an Interconnect Device

1. A method of port numbering in an interconnect device, comprising: loading a port configuration value from a memory device; enabling one or more ports and subports according to the configuration value; assigning contiguous logical port numbers to the one or more ports and subports included in the interconnect device; receiving a mapping request; and providing a mapped response associated with the mapping request to an entity.

2. The method of claim 1 , wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

3. The method of claim 1 , wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

4. The method of claim 1 , wherein the mapping request is a logical port number and the mapped response is a physical port number.

5. The method of claim 1 , wherein the mapping request is a physical port number and the mapped response is a logical port number.

6. A system for port numbering in an interconnect device, comprising: means for loading a port configuration value from a memory device; means for enabling one or more ports and subports according to the configuration value; means for assigning contiguous logical port numbers to the one or more ports and subports included in the interconnect device; means for receiving a mapping request; and means for providing a mapped response associated with the mapping request to an entity.

7. The system of claim 6 , wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

8. The system of claim 6 , wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

9. The system of claim 6 , wherein the mapping request is a logical port number and the mapped response is a physical port number.

10. The system of claim 6 , wherein the mapping request is a physical port number and the mapped response is a logical port number.

11. An interconnect device comprising: a memory device; and a preprocessor, wherein the preprocessor loads a port configuration value from the memory device; enables one or more ports and subports according to the configuration value; assigns contiguous logical port numbers to the one or more ports and subports included in the interconnect device; receives a mapping request; and provides a mapped response associated with the mapping request to an entity.

12. The interconnect device of claim 1 , wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

13. The interconnect device of claim 11 , wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

14. The interconnect device of claim 11 , wherein the mapping request is a logical port number and the mapped response is a physical port number.

15. The interconnect device of claim 11 , wherein the mapping request is a physical port number and the mapped response is a logical port number.

16. A computer-readable storage medium having stored thereon a plurality of instructions, said plurality of instructions when executed, causing said computer to perform: loading a port configuration value from a memory device; enabling one or more ports and subports according to the configuration value; assigning contiguous logical port numbers to the one or more ports and subports included in the interconnect device; receiving a mapping request; and providing a mapped response associated with the mapping request to an entity.

17. The computer-readable medium of claim 16 , wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

18. The computer-readable medium of claim 16 , wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

19. The computer-readable medium of claim 16 , wherein the mapping request is a logical port number and the mapped response is a physical port number.

20. The computer-readable medium of claim 16 , wherein the mapping request is a physical port number and the mapped response is a logical port number.