Latching Electronic Circuit for Random Number Generation

1. A physical random number generator, comprising: a hi-stable latch; a voltage source operable to provide one or more voltage input signals for provoking said bi-stable latch into a metastable state wherein the voltage source includes a voltage divider to generate a first voltage input signal; and a clock operable to provide a clock signal for triggering said bi-stable latch, wherein said bi-stable latch is operable to latch a random number bit in response to a triggering of said bi-stable latch by the clock signal, the random number bit being a function of a provoking of said bi-stable latch into the metastable state by the one or more voltage input signals.

2. The physical random number generator of claim 1 , wherein the clock signal intensifies the metastable state of said bi-stable latch.

3. The physical random number generator of claim 1 , wherein said bi-stable latch is a flip-flop including a data input for receiving a first voltage input signal, and a clock input for receiving the clock signal.

4. A physical random number generating system, comprising: a plurality of random number generators operable to provide a plurality of random number bits; a logic circuit operable to provide a system random number bit in response to a reception of the plurality of random number bits; and wherein a first random number generator includes a bi-stable latch, a voltage source operable to provide one or more voltage input signals for provoking said bi-stable latch into a metastable state wherein the voltage source includes a voltage divider operable to generate a first voltage input signal, and a clock operable to provide a clock signal for triggering said bi-stable latch, wherein said bi-stable latch is operable to latch a first random number bit in response to a triggering of bi-stable latch by the clock signal, the random number bit being a function of a provoking of said bi-stable latch into the metastable state by the one or more voltage input signals.

5. The physical random number generating system of claim 4 , wherein the clock signal intensifies the metastable state of said bi-stable latch.

6. The physical random number generating system of claim 4 , wherein said bi-stable latch is a flip-flop including a data input for receiving a first voltage input signal, and a clock input for receiving the clock signal.

7. A method of operating a bi-stable latch of a physical random number generator, said method comprising: receiving one or more voltage input signals for provoking the bi-stable latch into a metastable state wherein said voltage source includes a voltage divider operable to generate a first voltage input signal; receiving a clock signal for triggering the bi-stable latch; and latching a random number bit in response to triggering of the bi-stable latch, the random number bit being a function of a provoking of the bi-stable latch into the metastable state by the one or mare voltage input signals.

8. The method of claim 7 , further comprising: providing the random number bit to a logic circuit whereby a system random number bit is generated as a function of the random number bit.