Method and Apparatus for Loop Detection Utilizing Multiple Loop Counters and a Branch Promotion Scheme

1. A method comprising: executing a branch instruction; updating a plurality of event counts corresponding to said branch instruction in response to said executing; determining a loop behavior status corresponding to said branch instruction in response to said updating; and promoting said branch instruction to a loop branch prediction type in response to said determining a loop behavior status; wherein said plurality of event counts comprises a branch execution count, a branch taken count, and a branch transition count; and wherein said determining a loop behavior status comprises detecting the relationship C exec =C taken +ceil(C transition /2) in response to a branch misprediction, wherein C exec corresponds to said branch execution count, C taken corresponds to said branch taken count, and C transition corresponds to said branch transition count, and wherein ceil(N) specifies a smallest integer greater than or equal to N.

2. The method as recited in claim 1 , further comprising: determining a non-loop behavior status corresponding to said branch instruction in response to said promoting; and demoting said branch instruction to a non-loop branch prediction type in response to said determining a non-loop behavior status.

3. The method as recited in claim 1 , wherein said promoting comprises: clearing said branch execution count; computing a loop period value; and storing said loop period value.

4. The method as recited in claim 3 , further comprising: incrementing said branch execution count in response to an execution of said branch instruction; comparing said branch execution count to said stored loop period value; and predicting a final loop iteration in response to said comparing.

5. The method as recited in claim 2 , wherein said determining a non-loop behavior status comprises detecting a branch misprediction.

6. The method as recited in claim 2 , wherein said demoting comprises selecting a non-loop branch prediction technique corresponding to said branch instruction.

7. The method as recited in claim 1 , further comprising: detecting an overflow of said branch execution count; and dividing each of said branch execution count, said branch taken count, and said branch transition count by a given value in response to said detecting an overflow.

8. The method as recited in claim 7 , wherein each of said branch execution count, said branch taken count, and said branch transition count is represented as a binary number, and wherein said dividing comprises a logical right shift operation by one or more binary digit positions.

9. A branch processing unit comprising: a plurality of event counters corresponding to a branch instruction and configured to be updated in response to execution of said branch instruction; and branch control logic coupled to said plurality of event counters, wherein said branch control logic is configured to determine a loop behavior status corresponding to said branch instruction in response to said updating and further configured to promote said branch instruction to a loop branch prediction type in response to said determining a loop behavior status; wherein said plurality of event counters comprises a branch execution counter, a branch taken counter, and a branch transition counter, each configured to store a respective value; and wherein to determine said loop behavior status, said branch control logic is further configured to detect the relationship C exec =C taken +ceil(C transition /2) in response to a branch misprediction, wherein C exec corresponds to a value stored in said branch execution counter, C taken corresponds to a value stored in said branch taken counter, and C transition corresponds to a value stored in said branch transition counter, and wherein ceil(N) specifies a smallest integer greater than or equal to N.

10. The branch processing unit as recited in claim 9 , wherein said branch control logic is further configured to determine a non-loop behavior status corresponding to said branch instruction in response to said promoting and to demote said branch instruction to a non-loop branch prediction type in response to said determining a non-loop behavior status.

11. The branch processing unit as recited in claim 9 , wherein to promote said branch instruction, said branch control logic is further configured to: clear said branch execution counter; clear a loop period value; and store said loop period value in one of said branch taken counter or said branch transition counter.

12. The branch processing unit as recited in claim 11 , wherein said branch execution counter is configured to increment in response to an execution of said branch instruction; and wherein said branch control logic is configured to compare a value stored in said branch execution counter to said stored loop period value and to predict a final loop iteration in response to said comparing.

13. The branch processing unit as recited in claim 10 , wherein to determine a non-loop behavior status, said branch control logic is further configured to detect a branch misprediction.

14. The branch processing unit as recited in claim 10 , wherein to demote said branch instruction, said branch control logic is further configured to select a non-loop branch prediction technique corresponding to said branch instruction.

15. The branch processing unit as recited in claim 9 , wherein said branch execution counter is further configured to detect an overflow, and wherein each of said branch execution counter, said branch taken counter, and said branch transition counter is configured to divide said respective stored value by a given value in response to said detecting an overflow.

16. The branch processing unit as recited in claim 15 , wherein each said respective stored value comprises a binary number, and wherein said dividing comprises a logical right shift operation by one or more binary digit positions.

17. A microprocessor comprising: an execution unit configured to execute instructions; and a branch processing unit coupled to said execution unit and configured to: update a plurality of event counts corresponding to a branch instruction in response to execution of said branch instruction; determine a loop behavior status corresponding to said branch instruction in response to said updating; and promote said branch instruction to a loop branch prediction type in response to said determining a loop behavior status; wherein said plurality of event counts comprises a branch execution count, a branch taken count, and a branch transition count, and wherein to determine said loop behavior status, said branch prediction unit is further configured to detect the relationship C exec =C taken +ceil(C transition /2) in response to a branch misprediction, wherein C exec corresponds to said branch execution count, C taken corresponds to said branch taken count, and C transition corresponds to said branch transition count, and wherein ceil(N) specifies a smallest integer greater than or equal to N.

18. The microprocessor as recited in claim 17 , wherein said branch prediction unit is further configured to: determine a non-loop behavior status corresponding to said branch instruction in response to said promoting; and demote said branch instruction to a non-loop branch prediction type in response to said determining a non-loop behavior status.

19. The microprocessor as recited in claim 17 , wherein to promote said branch instruction, said branch prediction unit is further configured to: clear said branch execution count; compute a loop period value; and store said loop period value.

20. The microprocessor as recited in claim 19 , wherein said branch prediction unit is further configured to: increment said branch execution count in response to an execution of said branch instruction; compare said branch execution count to said stored loop period value; and predict a final loop iteration in response to said comparing.