Integrated Clock and Input Output Placer

1. A method of placing a circuit design comprising the steps of: (a) assigning initial locations on an integrated circuit to inputs and outputs of the circuit design; (b) selecting a component type used in the circuit design; (c) generating a cost function corresponding to the inputs and outputs and the selected component type; (d) annealing the selected component type using the cost function; (e) determining location constraints for the inputs and outputs and the selected component type according to said step (d); and (f) repeating steps (b)–e) for additional component types such that location constraints determined for each additional component type do not violate location constraints determined for prior component types.

2. The method of claim 1 , wherein the at least one component type is selected from a group consisting of inputs and outputs, local clock sources, and global clock sources.

3. The method of claim 1 , wherein the selected component type includes inputs and outputs or local clock sources, and wherein the additional component types include global clock sources.

4. The method of claim 3 , said step (d) further comprising the step of assigning locations to global clock sources.

5. The method of claim 4 , said step (e) further comprising the step of constraining loads of global clock sources to windows of the integrated circuit.

6. The method of claim 1 , said step (d) further comprising the step of assigning individual inputs and outputs to input/output banks of the integrated circuit.

7. The method of claim 1 , said step (d) further comprising the step of assigning locations to local clock sources.

8. The method of claim 7 , said step (e) further comprising the step of constraining loads of local clock sources to windows of the integrated circuit.

9. A method of placing a circuit design comprising the steps of: (a) assigning initial locations on an integrated circuit to inputs and outputs of the circuit design; (b) selecting at least two different component types used in the circuit design; (c) generating a cost function corresponding to the inputs and outputs and each selected component type; (d) annealing the selected component types of the circuit design simultaneously using the cost function; and (e) determining location constraints for the circuit design according to said step (d).

10. The method of claim 9 , said step (b) further comprising the step of selecting inputs and outputs, local clock sources, and global clock sources.

11. The method of claim 10 , said step (d) further comprising the steps of: assigning individual inputs and outputs to input/output banks of the integrated circuit; assigning locations to local clock sources; and assigning locations to global clock sources.

12. The method of claim 11 , said step (e) further comprising the steps of: constraining loads of local clock sources to windows of the integrated circuit; and constraining loads of global clock sources to windows of the integrated circuit.

13. A system for placing a circuit design comprising the steps of: means for assigning initial locations on an integrated circuit to inputs and outputs of the circuit design; means for selecting a component type used in the circuit design; means for generating a cost function corresponding to the inputs and outputs and the selected component type; means for annealing the inputs and outputs and the selected component type using the cost function; means for determining location constraints for the selected component type according to said annealing step; and means for causing said means for assigning, means for selecting, means for generating, means for annealing, and means for determining to operate on additional component types such that location constraints determined for each additional component type do not violate design constraints determined for prior component types.

14. The system of claim 13 , wherein the component types are selected from the group consisting of inputs and outputs, local clock sources, and global clock sources.

15. The system of claim 14 , wherein the selected component types include inputs and outputs and local clock sources.

16. The system of claim 15 , wherein the additional component types include global clock sources.

17. The system of claim 16 , wherein said means for annealing further comprise means for assigning locations to global clock sources.

18. The system of claim 15 , wherein said means for annealing further comprise means for assigning individual inputs and outputs to input/output banks of the circuit design.

19. The system of claim 15 , wherein said means for annealing further comprise means for assigning locations to local clock sources.

20. The system of claim 19 , wherein said means for determining further comprise means for constraining loads of local clock sources to windows of the integrated circuit.

21. The system of claim 17 , wherein said means for determining further comprise means for constraining loads of global clock sources to windows of the integrated circuit.

22. A system for placing a circuit design comprising the steps of: means for assigning initial locations on an integrated circuit to inputs and outputs of the circuit design; means for selecting at least two different component types used in the circuit design; means for generating a cost function corresponding to the inputs and outputs and each selected component type; means for annealing the inputs and outputs and the selected component types of the circuit design simultaneously using the cost function; and means for determining location constraints for the circuit design according to said annealing step.

23. The system of claim 22 , wherein said means for selecting select inputs and outputs, local clock sources, and global clock sources.

24. The system of claim 23 , wherein said means for annealing further comprise: means for assigning individual inputs and outputs to input/output banks of the integrated circuit; means for assigning locations to local clock sources; and means for assigning locations to global clock sources.

25. The system of claim 24 , wherein said means for determining further comprise: means for constraining loads of local clock sources to windows of the integrated circuit; and means for constraining loads of global clock sources to windows of the integrated circuit.

26. A machine readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the steps of: (a) assigning initial locations on an integrated circuit to inputs and outputs of the circuit design; (b) selecting component type used in the circuit design; (c) generating a cost function corresponding to the inputs and outputs and the selected component type; (d) annealing the inputs and outputs and the selected component type using the cost function; (e) determining location constraints for the inputs and outputs and the selected component type according to said step (d); and (f) repeating steps (b)–(e) for additional component types such that location constraints determined for each additional component type do not violate location constraints determined for prior component types.

27. The machine readable storage of claim 26 , wherein the component types are selected from the group consisting of inputs and outputs, local clock sources, and global clock sources.

28. The machine readable storage of claim 27 , wherein the selected component types include inputs and outputs and local clock sources.

29. The machine readable storage of claim 28 , wherein the additional component types include global clock sources.

30. The machine readable storage of claim 29 , said step (d) further comprising the step of assigning locations to global clock sources.

31. The machine readable storage of claim 30 , said step (e) further comprising the step of constraining loads of global clock sources to windows of the integrated circuit.

32. The machine readable storage of claim 28 , said step (d) further comprising the step of assigning individual inputs and outputs to input/output banks of the integrated circuit.

33. The machine readable storage of claim 28 , said step (d) further comprising the step of assigning locations to local clock sources.

34. The machine readable storage of claim 33 , said step (e) further comprising the step of constraining loads of local clock sources to windows of the integrated circuit.

35. A machine readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the steps of: (a) assigning initial locations on an integrated circuit to inputs and outputs of the circuit design; (b) selecting at least two different component types used in the circuit design; (c) generating a cost function corresponding to the inputs and outputs and each selected component type; (d) annealing the inputs and outputs and the selected component types of the circuit design simultaneously using the cost function; and (e) determining location constraints for the circuit design according to said step (d).

36. The machine readable storage of claim 35 , said step (b) further comprising the step of selecting inputs and outputs, local clock sources, and global clock sources.

37. The machine readable storage of claim 36 , said step (d) further comprising the steps of: assigning individual inputs to input/output banks of the circuit design; assigning locations to local clock sources; and assigning locations to global clock sources.

38. The machine readable storage of claim 37 , said step (e) further comprising the steps of: constraining loads of local clock sources to windows of the integrated circuit; and constraining loads of global clock sources to windows of the integrated circuit.