Method and Apparatus for an Energy Efficient Operation of Multiple Processors in a Memory

1. A semiconductor device comprising: (a) a memory array comprising a plurality of dynamic random access memory storage elements, word lines and bit lines connected to the dynamic random access memory storage elements and sense amplifiers connected to the bit lines; (b) processor elements coupled to a plurality of sense amplifiers, said processor elements comprising arithmetic logic units each performing the same computational operation; (c) a row decoder connected to the word lines; (d) a column decoder connected to the plurality of processor elements; (e) a plurality of pins for receiving and transmitting data and/or instructions; (f) a control bus coupling the pins to the column decoder and the row decoder for providing direct access to and from the pins to the memory array.

2. The semiconductor device according to claim 1 , wherein said row decoder and said column decoder comprise a latch.

3. The semiconductor device according to claim 1 , wherein the pins receive and transmit data to and from a processor.

4. The semiconductor device according to claim 1 , wherein the pins receive and transmit data to and from a central processing unit.

5. The semiconductor device according to claim 1 , wherein the pins receive and transmit data to and from a memory array in another semiconductor device.

6. The semiconductor device according to claim 1 , wherein a plurality of the processor elements are programmable so as to perform a computational operation.

7. The semiconductor device according to claim 6 , wherein the computational operation comprises a self-test operation.

8. The semiconductor device according to claim 1 , wherein the number of processor elements is less than or equal to the number of sense amplifiers.

9. The semiconductor device according to claim 1 , further comprising means for providing an instruction to a plurality of the processor elements.

10. A semiconductor device comprising: (a) a memory array comprising a plurality of dynamic random access memory storage elements, word lines and bit lines connected to the dynamic random access memory storage elements and sense amplifiers connected to the bit lines; (b) processor elements coupled to a plurality of sense amplifiers, said processor elements comprising dynamic logic multiplexers each performing the same computational operation; (c) a row decoder connected to the word lines; (d) a column decoder connected to the plurality of processor elements; (e) a plurality of pins for receiving and transmitting data and/or instructions; (f) a control bus coupling the pins to the column decoder and the row decoder for providing direct access to and from the pins to the memory array.

11. The semiconductor device according to claim 10 , wherein said row decoder and said column decoder comprise a latch.

12. The semiconductor device according to claim 10 , wherein the pins receive and transmit data to and from a processor.

13. The semiconductor device according to claim 10 , wherein the pins receive and transmit data to and from a central processing unit.

14. The semiconductor device according to claim 10 , wherein the pins receive and transmit data to and from a memory array in another semiconductor device.

15. The semiconductor device according to claim 10 , wherein a plurality of the processor elements are programmable so as to perform a computational operation.

16. The semiconductor device according to claim 15 , wherein the computational operation comprises a self-test operation.

17. The semiconductor device according to claim 10 , further comprising means for providing an instruction to a plurality of the processor elements.

18. The semiconductor device according to claim 10 , wherein the number of processor elements is less than or equal to the number of sense amplifiers.

19. A semiconductor device comprising: (a) a memory array comprising a plurality of dynamic random access memory storage elements, word lines and bit lines connected to the dynamic random access memory storage elements and sense amplifiers connected to the bit lines; (b) processor elements coupled to a plurality of sense amplifiers, said processor elements being programmable so as to perform the same computational operations, said computational operations comprising a self-test operation; (c) a row decoder connected to the word lines; (d) a column decoder connected to the plurality of processor elements; (e) a plurality of pins for receiving and transmitting data and/or instructions; (f) a control bus coupling the pins to the column decoder and the row decoder for providing direct access to and from the pins to the memory array.

20. The semiconductor device according to claim 19 , wherein the pins receive and transmit data to and from a processor.

21. The semiconductor device according to claim 19 , wherein the pins receive and transmit data to and from a central processing unit.

22. The semiconductor device according to claim 19 , wherein the pins receive and transmit data to and from a memory array in another semiconductor device.