Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic shelf comprising: a plurality of system circuit boards; a first system circuit board containing a first central processing unit (CPU) providing decision-making intelligence for end-user services supported by the first system circuit board; an auxiliary circuit board connected to the first circuit board; means contained on the auxiliary circuit board for providing input and output communications between the CPU and devices external to both the first system circuit board and auxiliary circuit board, at least some of said devices comprising sensors that sense parameters related to management control of the electronic shelf; said CPU being solely responsible for decision-making intelligence for management control for at least a predetermined number of system circuit boards while also being responsible for the decision-making intelligence for end-user services directly supported by the first system circuit board.
2. The electronic shelf of claim 1 further comprising a first connector connected to the first system circuit board and the auxiliary circuit board for coupling signals therebetween.
3. The electronic shelf of claim 1 wherein the electronic shelf and the system circuit boards conform to physical standards of the Advanced Telecom Computing Architecture.
4. The electronic shelf of claim 2 wherein the auxiliary circuit board is a rear transition module.
5. The electronic shelf of claim 4 further comprising a midplane, the first connector supported by the midplane and disposed to concurrently connect the first system circuit board and the auxiliary circuit board.
6. The electronic shelf of claim 2 wherein the auxiliary circuit board is a mezzanine board.
7. The electronic shelf of claim 6 further comprising a midplane, the first connector supported by the midplane and disposed to concurrently connect the first system circuit board and the auxiliary circuit board.
8. A method for providing management control of an electronic shelf having a plurality of system circuit boards comprising the steps of: executing decisions for end-user services supported by a first system circuit board by utilizing a first central processing unit (CPU) on the first system circuit board; providing input and output communications via an auxiliary circuit board connected to the first circuit board, said communications being between the CPU and devices external to both the first system circuit board and auxiliary circuit board, at least some of said devices sensing parameters related to management control of the electronic shelf; employing only the CPU on the first system circuit board for decision-making intelligence for management control for at least a predetermined number of system circuit boards while also using the CPU to execute decisions for end-user services supported by the first system circuit board.
9. The method of claim 8 wherein the auxiliary circuit board conforms with the physical requirements for a rear transition module in accord with physical standards of the Advanced Telecom Computing Architecture.
10. The method of claim 9 further comprising the steps of employing a midplane, the first connector being supported by the midplane and disposed to concurrently connect the first system circuit board and the auxiliary circuit board.
11. The method of claim 8 wherein the predetermined number of system circuit boards comprises the first system circuit board and at least two other system circuit boards.
12. The electronic shelf of claim 1 wherein the CPU is solely responsible for decision-making intelligence for management control where management control comprises control of maintenance functions of the predetermined number of system circuit boards.
13. The electronic shelf of claim 12 wherein the CPU is solely responsible for decision-making intelligence for management control where management control comprises control of maintenance functions where sensor information of maintenance functions on the predetermined number of system circuit boards is received and processed by the CPU.
Unknown
January 2, 2007
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