High-Speed Interface Circuit for Semiconductor Memory Chips and Memory System Including Semiconductor Memory Chips

1. A high-speed interface circuit implemented in a semi-conductor memory chip including a memory core, the high-speed interface circuit comprising: a first interface circuit section connectable to a write data-/command and address bus and including: a serial input terminal to receive a serial stream of write data-/command and address signals from a serial output terminal of a corresponding first interface circuit section of a preceding same memory chip or from a serial output terminal of a memory controller, the serial input terminal further being connected to: a write data-/command and address re-driver/-transmitter path arranged to re-drive the serial stream of write data-/command and address signals to a serial output terminal of the write data-/command and address re-driver/-transmitter path and connectable to a serial input terminal of a corresponding first interface circuit of a next same memory chip; and a main write signal path arranged between the serial input terminal and a parallel output terminal and including serial-to-parallel conversion and synchronization means for serial-to-parallel converting and synchronizing with a reference clock signal the write data-/command and address signals received at the serial input terminal and delivering the serial-to-parallel converted and synchronized write data-/command and address signals to the parallel output terminal of the first interface circuit section and from the parallel output terminal of the first interface circuit to the memory core; and a second interface circuit section connectable to a read data bus and including: a parallel read data input terminal connected to the memory core to receive parallel read data from the memory core; a serial read data input terminal connected to receive a serial read data stream from a serial read data output terminal of a corresponding second interface circuit section of a preceding same memory chip and arranged to re-drive the received serial read data stream through a read data re-driver/receiver path to a serial read data output terminal of the second interface circuit section; and a main read signal path connected between the parallel read data input terminal and the serial read data output terminal of the second interface circuit section and having means for inserting the parallel-to-serial converted read data read from the memory core and received at a parallel input terminal of the main read signal path into the serial read data stream from the serial read data input terminal, synchronizing the serial read data stream with a reference clock signal and providing the serialized read data stream to the serial read data output terminal connectable with the read data bus to a serial read data input terminal of a corresponding second interface circuit section of a next same memory chip or to a serial read data input terminal of the memory controller; wherein the first and second interface circuit sections further include a reference clock receiving terminal to receive the reference clock signal.

2. The high-speed memory interface circuit of claim 1 , wherein the write data-/command and address signal re-driver/transmitter path of the first interface circuit section includes a transparent write signal re-driving/transmitting section without a clock signal synchronizing circuitry.

3. The high-speed memory interface circuit of claim 1 , wherein the read data re-driver/transmitter path of the second interface circuit section includes a transparent read signal re-driving transmitting section without a clock signal synchronizing circuitry.

4. The high-speed interface circuit of claim 1 , wherein the write data-/command and address signal re-driver/transmitter path of the first interface circuit section includes synchronized write signal re-driving/transmitting and synchronization means for synchronizing the re-driven write data-/command and address signals with the reference clock signal.

5. The high-speed interface circuit of claim 1 , wherein the read data re-driver/transmitter path of the second interface circuit section includes synchronized read signal re-driver/transmitting and synchronization means for synchronizing the re-driven read signals with the reference clock signal.

6. The high-speed interface circuit of claim 2 , wherein the write data-/command and address signal re-driver/transmitter path of the first interface circuit section further includes a first switching device arranged to receive the serial write data-/command and address stream before the serial output terminal of the first interface circuit section, the first switching device being controlled by an external control signal from the memory controller or by a control signal included in the protocol of the write data-/command and address signal stream to selectively switch between the transparent write signal re-driving/transmitting section and the synchronized write signal re-driver/transmitter means.

7. The high-speed interface circuit of claim 3 , wherein the second interface circuit section further includes first switching device arranged before the serial output terminal of the second interface circuit section, the first switching device being controlled by a control signal included in the protocol of the write data-/command and address signal or by an external signal from the memory controller to selectively switch between the transparent read signal re-driving transmitting section and the synchronized read signal re-driver/transmitting and synchronization means.

8. The high-speed interface circuit of claim 1 , wherein the first interface circuit section includes: a bit synchronization unit arranged after the serial input terminal to sample and bit-synchronize the serial stream of write data-/command and address signals according to the reference clock signal; an even-odd bit alignment unit serially connected after the bit synchronization unit and configured to buffer the serial write data-/command and address signals synchronized and sampled by the bit synchronization unit and align the sampled even and odd signals synchronously with the reference clock signal; a serial-to-parallel converter unit serially connected after the even-odd bit alignment unit and configured to convert the serial write data-/command and address signals buffered and aligned by the even/odd bit alignment unit into a parallel data stream having an arbitrary data width; and a data delivery FIFO-unit connected after the serial-to-parallel converter unit at the parallel output terminal and configured to deliver the parallel data stream to the memory core synchronized with an internal clock rate of the memory core and compensating for different data skews and drifts.

9. The high-speed interface circuit of claim 8 , wherein the bit synchronization unit, the even-odd alignment unit, the serial-to-parallel converter unit and the data delivery FIFO-unit are consecutively arranged such that each unit supplies the reference clock signal synchronized by the bit synchronization unit with the serial write data-/command and address signal stream to the next consecutive unit together with each of the supplied write data-/command and address signals.

10. The high-speed interface circuit of claim 8 , wherein the first interface circuit section further includes: a drift compensation FIFO-unit serially connected after the even-odd bit alignment unit and configured to compensate phase drift of the even-odd bit aligned serial write data-/command and address signals in synchronism with the reference clock signal; and a 2:1-serializer serially arranged after the drift compensation FIFO-unit.

11. The high-speed interface circuit of claim 10 , wherein the bit synchronization unit and the even-odd bit alignment unit are each respectively arranged to supply the reference clock signal synchronized by the bit synchronization unit with the serial write data-/command and address signal stream to the next consecutive unit together with each of the supplied write data-/command and address signals.

12. The high-speed interface circuit of claim 10 , wherein a data input of the serial-to-parallel converter unit is connected to an output of the drift compensation FIFO-unit.

13. The high-speed interface circuit of claim 10 , wherein a data input of the serial-to-parallel converter unit is connected to an output of the even-odd bit alignment unit.

14. The high-speed interface circuit of claim 8 , wherein the first interface circuit section further includes: a drift compensation FIFO-unit serially connected after the even-odd bit alignment unit and configured for compensating phase drift of the even-odd bit aligned serial write data-/command and address signals in synchronism with the reference clock signal; a de-emphasis FIR-unit serially connected after the drift compensation FIFO and configured for channel adaptation to compensate for intersymbol interference; and a 2:1 serializer serially connected after the de-emphasis FIR-unit.

15. The high-speed interface circuit of claim 14 , wherein the bit synchronization unit and the even-odd bit alignment unit are each respectively configured to supply the reference clock signal synchronized by the bit synchronization unit with the serial write data-/command and address signal stream to the next consecutive unit together with each of the supplied write data-/command and address signals.

16. The high-speed interface circuit of claim 14 , wherein a data input of the serial-to-parallel converter unit is connected to an output of the drift compensation FIFO-unit.

17. The high-speed interface circuit of claim 14 , wherein the de-emphasis FIR-unit and the drift compensation FIFO-unit are combined and a data input of the serial-to-parallel converter unit is connected to an output of the de-emphasis FIFO-unit.

18. The high-speed interface circuit of claim 8 , wherein the drift compensation FIFO-unit has a depth according to plural symbol sequences of the serial write data-/command and address signals.

19. The high-speed interface circuit of claim 8 , wherein the de-emphasis FIR-unit is switched on/off by an external signal from the memory controller.

20. The high-speed interface circuit of claim 1 , wherein, in the main read signal path, the second interface circuit section includes: a read FIFO-unit arranged at the parallel read data input terminal to adapt a data rate of data read from the memory core to a clock domain of the second interface circuit section; a parallel-to-serial converter unit connected after the read FIFO-unit and configured to achieve parallel-to-serial conversion of the read data and to convert the clock rate of the read data to the clock rate of the reference clock; a de-emphasis FIR-unit serially connected after the parallel-to-serial converter circuit and configured to compensate for intersymbol interference; and a 2:1 serializer serially arranged after the de-emphasis FIR-unit.

21. The high-speed interface circuit of claim 20 , wherein the de-emphasis FIR-unit is switched on/off by an external signal from the memory controller.

22. The high-speed interface circuit of claim 20 , wherein the de-emphasis FIR-unit is configured to receive the reference clock signal and supply the reference clock signal to the parallel-to-serial converter unit, and parallel-to-serial converter unit is configured to supply the reference clock signal to the read FIFO-unit.

23. The high-speed interface circuit of claim 20 , wherein the read data re-driver/transmitter path of the second interface circuit section includes: a transparent read signal re-driving/transmitting device without any clock signal synchronizing circuitry; synchronized read data re-driver/transmitting and synchronization means for synchronizing the re-driven read signals with the reference clock signal; and a first switching device arranged immediately before the serial output terminal of the second interface circuit section, the first switching device being controlled by a control bit included in the protocol of the write data-/command and address signals or by an external signal from the memory controller to selectively switch between the transparent read signal re-driving/transmitting device and the synchronized read data re-driver/transmitter means; wherein the synchronized read data re-driver/transmitter and synchronization means further includes: a bit synchronization unit serially connected after the serial read data input terminal configured to sample and bit-synchronize the serial stream of read data with the reference clock signal; an even-odd bit alignment unit serially connected after the bit synchronization unit and configured to buffer the serial read data signals synchronized and sampled by the bit synchronization unit and align the serial read data signals synchronously to the reference clock signal; a drift compensation FIFO-unit serially connected after the even-odd bit alignment unit and configured to compensate phase drift of the even-odd bit aligned read data signals in synchronism with the reference clock signal; a second switching device inserted between the drift compensation FIFO-unit, the parallel-to-serial converter unit and the de-emphasis FIR-unit of the main read signal path and configured to switch between the synchronized re-driven read data signals and the parallel-to-serial converted read data signals in synchronism with the reference clock signal and to insert the parallel-to-serial converted read data signals into the read data signal stream; the de-emphasis FIR-unit; the 2:1 serializer of the main read signal path; and the first switching device.

24. The high-speed interface circuit of claim 23 , wherein the bit synchronization unit and the even-odd bit alignment unit are each respectively configured to supply the reference clock signal synchronized by the bit synchronization unit with the serial read data stream from the serial read data input terminal to the next consecutive unit together with each of the supplied read data signals.

25. The high-speed interface circuit of claim 23 , wherein the drift compensation FIFO-unit and the parallel-to-serial converter unit are configured to belong to the same clock domain.

26. The high-speed interface circuit of claim 1 , wherein the clock rate of the reference clock signal is selected from the group consisting of: one half of the clock rate of a memory system clock, one third of the clock rate of a memory system clock, one quarter of the clock rate of a memory system clock, and equal to the clock rate of a memory system clock.

27. A semiconductor memory chip including a memory core and a high-speed interface circuit, the high-speed interface circuit comprising: a first interface circuit section connectable to a write data-/command and address bus and including: a serial input terminal to receive a serial stream of write data-command and address signals from a serial output terminal of a corresponding first interface circuit section of a preceding same memory chip or from a serial output terminal of a memory controller, the serial input terminal further being connected to: a write data-/command and address re-driver/-transmitter path arranged to re-drive the serial stream of write data-/command and address signals to a serial output terminal of the write data-/command and address re-driver/-transmitter path and connectable to a serial input terminal of a corresponding first interface circuit of a next same memory chip; and a main write signal path arranged between the serial input terminal and a parallel output terminal and including serial-to-parallel conversion and synchronization means for serial-to-parallel converting and synchronizing with a reference clock signal the write data-/command and address signals received at the serial input terminal and delivering the serial-to-parallel converted and synchronized write data-/command and address signals to the parallel output terminal of the first interface circuit section and from the parallel output terminal of the first interface circuit to the memory core; and a second interface circuit section connectable to a read data bus and including: a parallel read data input terminal connected to the memory core to receive parallel read data from the memory core; a serial read data input terminal connected to receive a serial read data stream from a serial read data output terminal of a corresponding second interface circuit section of a preceding same memory chip and arranged to re-drive the received serial read data stream through a read data re-driver/receiver path to a serial read data output terminal of the second interface circuit section; and a main read signal path connected between the parallel read data input terminal and the serial read data output terminal of the second interface circuit section and having means for inserting the parallel-to-serial converted read data read from the memory core and received at a parallel input terminal of the main read signal path into the serial read data stream from the serial read data input terminal, synchronizing the serial read data stream with a reference clock signal and providing the serialized read data stream to the serial read data output terminal connectable with the read data bus to a serial read data input terminal of a corresponding second interface circuit section of a next same memory chip or to a serial read data input terminal of the memory controller; wherein the first and second interface circuit sections further include a reference clock receiving terminal to receive the reference clock signal.

28. The semiconductor memory chip of claim 27 , wherein the memory core comprises a dynamic RAM-memory core.

29. A semiconductor memory system including a plurality of semiconductor memory chips as recited in claim 27 , wherein the semiconductor memory chips are arranged on a memory module in a cascade of different memory ranks and connected by a write data-/command and address bus and a read data bus and in a point-to-point fashion to a memory controller.

30. The memory system of claim 29 , wherein the semiconductor memory chips and the write data-/command and address bus and the read data bus are arranged on the memory module and connected to the memory controller in a loop forward architecture.

31. The memory system of claim 29 , wherein the semiconductor memory chips and the write data-/command and address bus and the read data bus are arranged on the memory module and connected to the memory controller in a loop back architecture.

32. The memory system of claim 29 , wherein the semiconductor memory chips and the write data-/command and address bus and the read data bus are arranged on the memory module and connected to the memory controller in a ring architecture.