Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit for processing data, said integrated circuit comprising: a functional circuit operable to perform data processing operations; a diagnostic circuit operable to perform diagnostic operations upon said functional circuit; and an interface circuit operable to provide communication between said diagnostic circuit and an external diagnostic device; wherein said interface circuit is configured to use a bi-directional line carrying a bi-directional serial signal to transfer: (i) control signals from said external diagnostic device to said diagnostic circuit to control said diagnostic operations of said diagnostic circuit; and (ii) diagnostic data between said external diagnostic device and said diagnostic circuit.
2. The integrated circuit as claimed in claim 1 , wherein said diagnostic circuit is operable to perform one or more of: debugging operations; manufacturing test operations; manufacturing programming operations; and manufacturing configuration operations.
3. The integrated circuit as claimed in claim 1 , wherein said bi-directional line carrying the bi-directional serial signal is operable to communicate a pacing signal from said diagnostic circuit to said external diagnostic device, said pacing signal being operative to indicate whether or not said diagnostic circuit is ready for communication.
4. The integrated circuit as claimed in claim 3 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said diagnostic circuit forcing said bi-directional serial signal to a predetermined pacing level during a pacing signal time slot.
5. The integrated circuit as claimed in claim 3 , wherein said interface circuit is operable in a training mode to be responsive to a training signal of a predetermined form sent from said external diagnostic device to determine sample point timing for sampling said bi-directional serial signal and said pacing signal indicates that training has completed successfully.
6. The integrated circuit as claimed in claim 1 , wherein said bi-directional line carrying the bi-directional serial signal is operable to communicate a pacing signal from said diagnostic circuit to said external diagnostic device, said pacing signal being operative to indicate whether or not said diagnostic circuit has completed an operation.
7. The integrated circuit as claimed in claim 1 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said bi-directional line carrying the hi-directional serial signal being operable to communicate a start signal indicative of a start of a frame of serial data, said start signal being said bi-directional serial signal being driven to a predetermined start level to define a start signal time slot.
8. The integrated circuit as claimed in claim 7 , wherein said communication is held idle by said external diagnostic device holding said bi-directional serial signal at a level different to said predetermined start level and thereby delaying said start signal time slot until said bi-directional serial signal changes to said predetermined start level followed by a next frame of data being communicated.
9. The integrated circuit as claimed in claim 1 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said hi-directional line carrying the bi-directional serial signal being operable to communicate a stop signal indicative of an end of a frame of serial data, said stop signal being said hi-directional serial signal being driven to a predetermined stop level during a stop signal time slot.
10. The integrated circuit as claimed in claim 9 , wherein said diagnostic circuit uses receipt of a first part of said stop signal to indicate an abort of diagnostic operations.
11. The integrated circuit as claimed in claim 9 , wherein said diagnostic circuit uses receipt of a second part of said stop signal to confirm receipt of said frame of serial data by said diagnostic circuit.
12. The integrated circuit as claimed in claim 1 , wherein said interface circuit is operable in a non-clocked mode in which said communication is clocked in dependence upon transitions detected within said bi-directional serial signal.
13. The integrated circuit as claimed in claim 1 , wherein said interface circuit is operable in a training mode to be responsive to a training signal of a predetermined form sent from said external diagnostic device to determine sample point timing for sampling said bi-directional serial signal.
14. The integrated circuit as claimed in claim 13 , wherein said interface circuit initialises into said training mode.
15. The integrated circuit as claimed in claim 14 , wherein said initialisation follows a reset of said interface circuit.
16. The integrated circuit as claimed in claim 1 , wherein said diagnostic circuit comprises one or more of: (i) one or more scan chains operable to capture diagnostic data from said functional circuitry; (ii) one or more scan chains operable to apply diagnostic data to said functional circuitry; and (iii) one or more debug bus access circuits operable to provide communication via a bus within said functional circuit.
17. The integrated circuit as claimed in claim 1 , wherein said interface circuit is operable: (i) in a clocked mode in which said communication is clocked by a separate clock signal used by said integrated circuit; and (ii) in a non-clocked mode in which said communication is clocked in dependence upon transitions detected within said bi-directional serial signal.
18. The integrated circuit as claimed in claim 17 , wherein in said clocked mode, said communication is clocked by a clock signal being a multiple of a clock signal used by said integrated circuit.
19. The integrated circuit as claimed in claim 17 , wherein said interface circuit is operable to initialise in said non-clocked mode and is switchable to said clocked mode.
20. An integrated circuit for processing data, said integrated circuit comprising: a functional circuit operable to perform data processing operations; a diagnostic circuit operable to perform diagnostic operations upon said functional circuit; and an interlace circuit operable to provide communication between said diagnostic circuit and an external diagnostic device; wherein said interface circuit is configured to use a bi-directional line carrying a bi-directional serial signal to transfer: (i) control signals from said external diagnostic device to said diagnostic circuit to control said diagnostic operations of said diagnostic circuit; and (ii) diagnostic data between said external diagnostic device and said diagnostic circuit, wherein said bi-directional serial signal is operable to communicate a reset signal from said external diagnostic device to said diagnostic circuit, said reset signal being operative to reset said diagnostic circuit.
21. The integrated circuit as claimed in claim 20 , wherein said reset signal comprises said external diagnostic device holding said bi-directional serial signal carried on said bi-directional line at a predetermined reset level for a predetermined reset period.
22. A diagnostic device for performing diagnostic operations upon an integrated circuit, said diagnostic device comprising: an interface circuit operable to provide communication between said diagnostic device and a diagnostic circuit within said integrated circuit; wherein said interface circuit is configured to use a bi-directional line carrying a bi-directional serial signal coupled to a pin of said integrated circuit to transfer: (i) control signals from said diagnostic device to said integrated circuit to control diagnostic operations of performed by said integrated circuit; and (ii) diagnostic data between said diagnostic device and said integrated circuit.
23. The diagnostic device as claimed in claim 22 , wherein said diagnostic device is operable to control one or more of: debugging operations; manufacturing test operations; manufacturing programming operations; and manufacturing configuration operations.
24. The diagnostic device as claimed in claim 22 , wherein said bi-directional line carrying the bi-directional serial signal is operable to communicate a pacing signal from said diagnostic circuit to said diagnostic device, said pacing signal being operative to indicate whether or not said diagnostic circuit is ready for communication.
25. The diagnostic device as claimed in claim 24 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said diagnostic circuit forcing said bi-directional serial signal to a predetermined pacing level during a pacing signal time slot.
26. The diagnostic device as claimed in claim 24 , wherein said interface circuit is operable in a training mode to be responsive to a training signal of a predetermined form sent from said external diagnostic device to determine sample point timing for sampling said bi-directional serial signal and said pacing signal indicates that training has completed successfully.
27. The diagnostic device as claimed in claim 22 , wherein said bi-directional line carrying the bi-directional serial signal is operable to communicate a pacing signal from said diagnostic circuit to said external diagnostic device, said pacing signal being operative to indicate whether or not said diagnostic circuit has completed an operation.
28. The diagnostic device as claimed in claim 22 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said bi-directional line carrying the bi-directional serial signal being operable to communicate a start signal indicative of a start of a frame of serial data, said start signal being said bi-directional serial signal being driven to a predetermined start level to define a start signal time slot.
29. The diagnostic device as claimed in claim 28 , wherein said communication is held idle by said external diagnostic device holding said bi-directional serial signal at a level different to said predetermined start level and thereby delaying said start signal time slot until said bi-directional serial signal changes to said predetermined start level followed by a next frame of data being communicated.
30. The diagnostic device as claimed in claim 22 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said bi-directional line carrying the bi-directional serial signal being operable to communicate a stop signal indicative of an end of a frame of serial data, said stop signal being said bi-directional serial signal being driven to a predetermined stop level during a stop signal time slot.
31. The diagnostic device as claimed in claim 30 , wherein said diagnostic circuit uses receipt of a first part of said stop signal to indicate an abort of diagnostic operations.
32. The diagnostic device as claimed in claim 30 , wherein said diagnostic circuit uses receipt of a second part of said stop signal to confirm receipt of said frame of serial data by said diagnostic circuit.
33. The diagnostic device as claimed in claim 22 , wherein said interface circuit is operable in a non-clocked mode in which said communication is clocked in dependence upon transitions detected within said bi-directional serial signal.
34. The diagnostic device as claimed in claim 22 , wherein said interface circuit is operable in a training mode to be responsive to a training signal of a predetermined form sent from said external diagnostic device to determine sample point timing for sampling said bi-directional serial signal.
35. The diagnostic device as claimed in claim 34 , wherein said interface circuit initialises into said training mode.
36. The diagnostic device as claimed in claim 35 , wherein said initialisation follows a reset of said interface circuit.
37. The diagnostic device as claimed in claim 22 , wherein said diagnostic circuit comprises one or more of: (i) one or more scan chains operable to capture diagnostic data from said functional circuitry; (ii) one or more scan chains operable to apply diagnostic data to said functional circuitry; and (iii) one or more debug bus access circuits operable to provide communication via a bus within said functional circuit.
38. The diagnostic device as claimed in claim 22 , wherein said interface circuit is operable: (i) in a clocked mode in which said communication is clocked by a separate clock signal used by said integrated circuit; and (ii) in a non-clocked mode in which said communication is clocked in dependence upon transitions detected within said bi-directional serial signal.
39. The diagnostic device as claimed in claim 38 , wherein in said clocked mode, said communication is clocked by a clock signal being a multiple of a clock signal used by said integrated circuit.
40. The diagnostic device as claimed in claim 38 , wherein said interface circuit is operable to initialise in said non-clocked mode and is switchable to said clocked mode.
41. A diagnostic device for performing diagnostic operations upon an integrated circuit, said diagnostic device comprising: an interface circuit operable to provide communication between said diagnostic device and a diagnostic circuit within said integrated circuit; wherein said interface circuit is configured to use a bi-directional line carrying a bi-directional serial signal coupled to a pin of said integrated circuit to transfer: (i) control signals from said diagnostic device to said integrated circuit to control diagnostic operations of performed by said integrated circuit; and (ii) diagnostic data between said diagnostic device and said integrated circuit, wherein said bi-directional serial signal is operable to communicate a reset signal from said diagnostic device to said diagnostic circuit, said reset signal being operative to reset said diagnostic circuit.
42. The diagnostic device as claimed in claim 41 , wherein said reset signal comprises said diagnostic device holding said bi-directional serial signal carried by the bi-directional line at a predetermined reset level for a predetermined reset period.
43. A method of communicating with a diagnostic circuit operable to perform diagnostic operations upon an functional circuit within an integrated circuit, said method comprising the step of: using a bi-directional line carrying a bi-directional serial signal coupled to a pin of said integrated circuit to transfer: (i) control signals from an external diagnostic device to said diagnostic circuit to control said diagnostic operations of said diagnostic circuit; and (ii) diagnostic data between said external diagnostic device and said diagnostic circuit.
44. The method as claimed in claim 43 , wherein said diagnostic circuit is operable to perform one or more of: debugging operations; manufacturing test operations; manufacturing programming operations; and manufacturing configuration operations.
45. The method as claimed in claim 43 , wherein said bi-directional serial signal is operable to communicate a pacing signal from said diagnostic circuit to said external diagnostic device, said pacing signal being operative to indicate whether or not said diagnostic circuit is ready for communication.
46. The method as claimed in claim 45 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said diagnostic circuit forcing said bi-directional serial signal to a predetermined pacing level during a pacing signal time slot.
47. The method as claimed in claim 45 , wherein said interface circuit is operable in a training mode to be responsive to a training signal of a predetermined form sent from said external diagnostic device to determine sample point timing for sampling said bi-directional serial signal and said pacing signal indicates that training has completed successfully.
48. The method as claimed in claim 43 , wherein said bi-directional line carrying the bi-directional serial signal is operable to communicate a pacing signal from said diagnostic circuit to said external diagnostic device, said pacing signal being operative to indicate whether or not said diagnostic circuit has completed an operation.
49. The method as claimed in claim 43 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said bi-directional line carrying he bi-directional serial signal being operable to communicate a start signal indicative of a start of a frame of serial data, said start signal being said bi-directional serial signal being driven to a predetermined start level to define a start signal time slot.
50. The method as claimed in claim 49 , wherein said communication is held idle by said external diagnostic device holding said bi-directional serial signal at a level different to said predetermined start level and thereby delaying said start signal time slot until said bi-directional serial signal changes to said predetermined start level followed by a next frame of data being communicated.
51. The method as claimed in claim 43 , wherein the bi-directional serial signal has a serial signal protocol comprising different time slots for communicating different signals, said bi-directional line carrying the bi-directional serial signal being operable to communicate a stop signal indicative of an end of a frame of serial data, said stop signal being said bi-directional serial signal being driven to a predetermined stop level during a stop signal time slot.
52. The method as claimed in claim 51 , wherein said diagnostic circuit uses receipt of a first part of said stop signal to indicate an abort of diagnostic operations.
53. The method as claimed in claim 51 , wherein said diagnostic circuit uses receipt of a second part of said stop signal to confirm receipt of said frame of serial data by said diagnostic circuit.
54. The method as claimed in claim 43 , wherein said interface circuit is operable in a non-clocked mode in which said communication is clocked in dependence upon transitions detected within said bi-directional serial signal.
55. The method as claimed in claim 43 , wherein said interface circuit is operable in a training mode to be responsive to a training signal of a predetermined form sent from said external diagnostic device to determine sample point timing for sampling said bi-directional serial signal.
56. The method as claimed in claim 55 , wherein said interface circuit initialises into said training mode.
57. The method as claimed in claim 55 , wherein said initialisation follows a reset of said interface circuit.
58. The method as claimed in claim 43 , wherein said diagnostic circuit comprises one or more of: (i) one or more scan chains operable to capture diagnostic data from said functional circuitry; (ii) one or more scan chains operable to apply diagnostic data to said functional circuitry; and (iii) one or more debug bus access circuits operable to provide communication via a bus within said functional circuit.
59. The method as claimed in claim 43 , wherein said interface circuit is operable: (i) in a clocked mode in which said communication is clocked by a separate clock signal used by said integrated circuit; and (ii) in a non-clocked mode in which said communication is clocked in dependence upon transitions detected within said bi-directional serial signal.
60. The method as claimed in claim 59 , wherein in said clocked mode, said communication is clocked by a clock signal being a multiple of a clock signal used by said integrated circuit.
61. The method as claimed in claim 59 , wherein said interface circuit is operable to initialise in said non-clocked mode and is switchable to said clocked mode.
62. A method of communicating with a diagnostic circuit operable to perform diagnostic operations upon an functional circuit within an integrated circuit, said method comprising the step of: using a bi-directional line carrying a bi-directional serial signal coupled to a pin of said integrated circuit to transfer: (i) control signals from an external diagnostic device to said diagnostic circuit to control said diagnostic operations of said diagnostic circuit: and (ii) diagnostic data between said external diagnostic device and said diagnostic circuit, wherein said bi-directional serial signal is operable to communicate a reset signal from said external diagnostic device to said diagnostic circuit, said reset signal being operative to reset said diagnostic circuit.
63. The method as claimed in claim 62 , wherein said reset signal comprises said external diagnostic device holding said bi-directional serial signal at a predetermined reset level for a predetermined reset period.
Unknown
March 27, 2007
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