Method and Apparatus for Biased Identification of Potential Data Sharing Locations

1. A method for identifying predictable data sharing locations comprising: generating a testcase thread of code; creating a list of data lines used by said generated testcase thread of code; and generating a list of predictable data sharing locations available for testing data sharing capabilities of an integrated circuit, said list of predictable data sharing locations being generated based on said list of data lines used by said generated testcase thread of code; wherein said step of generating said list of predictable data sharing locations based on said list of data lines comprises: selecting a data line from said list of data lines used by said generated thread; and analyzing said data line for possible data sharing locations based on a bias hierarchy including checking for larger data sharing locations prior to checking for smaller data sharing locations.

2. A method for identifying predictable data sharing locations comprising: generating a testcase thread of code; creating a list of data lines used by said generated testcase thread of code; and generating a list of predictable data sharing locations based on said list of data lines used by said generated testcase thread of code; wherein said step of generating a list of predictable data sharing locations based on said list of data lines comprises: selecting a data line from said list of data lines used by said generated thread; and analyzing said data line for possible data sharing locations based on a bias hierarchy; wherein said bias hierarchy comprises: initially checking said data line for false data sharing store locations; and checking said data line for false data sharing load operations after said false data sharing store locations have been identified.

3. The method for identifying predictable data sharing locations of claim 2 , wherein said bias hierarchy further comprises checking for larger data sharing locations prior to checking for smaller data sharing locations.

4. The method for identifying predictable data sharing locations of claim 3 , wherein said method comprises instructions located in a testcase definition file.

5. A method for testing the data sharing capabilities of a processor under development comprising: selecting a test operation to be performed on said processor under development, said test operation being selected in accordance with a bias hierarchy specifying selecting false data sharing store operations prior to selecting false data sharing load operations; selecting a data sharing location from a list of false data sharing locations available for testing the data sharing capabilities of said processor under development; forming a testcase thread of code based on said selected test operation and said selected data sharing location; and using said testcase thread of code to test the data sharing capabilities of said processor under development.

6. The method for testing the data sharing capabilities of a processor under development of claim 5 , wherein said using step comprises: applying said testcase thread of code to a simulated model of said processor under development; applying said testcase thread to a microarchitecture model that defines the behavior of said processor under development; and comparing the results of applying said testcase thread of code to said simulation model of said integrated circuit design to the results of applying said testcase thread of code to said microarchitecture model.

7. The method of claim 6 , wherein said method further comprises: if said comparing results of said simulation model and said microarchitecture model result in different results, debugging said processor under development.

8. A method for testing the data sharing capabilities of a processor under development comprising: selecting a test operation to be performed on said processor under development; selecting a data sharing location from a list of available false data sharing locations; and forming a testcase thread of code based on said selected operation and said selected data sharing location; wherein said selecting a data sharing location from a list of available false data sharing locations comprises: selecting a first identified data sharing location from a list of possible data sharing locations; checking said data sharing location for compatibility with operation and size of said selected operation; and if selected identified data sharing location does not match the operation and size of said selected operation, selecting a second identified data sharing location from said list of possible data sharing locations.

9. The method of claim 8 , wherein a computer performs said method.

10. An apparatus for testing the correct behavior of an integrated circuit comprising: a processor; a memory storage unit; and a bus communicatively coupling said processor and said memory storage unit; wherein said memory storage unit includes a machine readable medium having instructions thereon for causing said apparatus to identify predictable data sharing locations available for testing the data sharing capabilities of said integrated circuit; wherein said identifying of said predictable data sharing locations available for testing the data sharing capabilities of said integrated circuit comprises a biased checking for larger data sharing locations prior to checking for smaller data sharing locations.

11. The apparatus for testing the correct behavior of an integrated circuit of claim 10 , wherein said integrated circuit comprises a processor under development.

12. An apparatus for testing the correct behavior of an integrated circuit comprising: a processor; a memory storage unit; and a bus communicatively coupling said processor and said memory storage unit; wherein said memory storage unit includes a machine readable medium having instructions thereon for causing said apparatus to identify predictable data sharing locations available for testing the data sharing capabilities of said integrated circuit, said integrated circuit comprising a processor under development; wherein said identifying of locations to test the data sharing capabilities of said processor under development comprises a bias based check method; wherein said bias based check method comprises: initially checking a data line for false data sharing store locations; and checking said data line for false data sharing load operations after said false data sharing store locations have been identified.

13. The apparatus for testing the correct behavior of an integrated circuit of claim 12 , wherein said bias based check method further comprises checking for larger data sharing locations prior to checking for smaller data sharing locations.

14. The apparatus for testing the correct behavior of an integrated circuit of claim 12 , wherein identifying locations to test the data sharing capabilities of said processor under development further comprises: generating a testcase thread of code; creating a list of data lines used by said generated testcase thread of code; and generating a list of predictable data sharing locations based on said list of data lines used by said generated testcase thread of code.

15. The apparatus for testing the correct behavior of an integrated circuit of claim 14 , wherein said apparatus generates additional testcase threads of code that perform predictable false data sharing based on said generated list of predictable data sharing locations.

16. A testcase generator capable of testing the data sharing capabilities of an integrated circuit comprising: a processor; a memory storage structure; and a bus communicatively coupling said processor and said memory; wherein said memory storage structure contains a machine readable medium having instructions thereon for causing said apparatus to identify predictable data sharing locations available for testing the data sharing capabilities of said integrated circuit; wherein said identifying of said predictable data sharing locations available for testing the data sharing capabilities of said integrated circuit comprises a biased checking for at least one false data sharing store location before checking for a false data sharing load location.

17. The testcase generator of claim 16 , wherein said testcase generator generates one or more data sharing testcases using said predictable data sharing locations.

18. An apparatus for testing the correct behavior of an integrated circuit comprising: computer processing means; memory means for storing data; and communications means for communicatively coupling said processing means and said memory means; wherein said memory means includes a machine readable medium having instructions thereon for causing said apparatus to identify predictable false data sharing locations available for testing the data sharing capabilities of said integrated circuit; wherein said identifying of said predictable data sharing locations available for testing the data sharing capabilities of said integrated circuit comprises a biased checking for at least one false data sharing store location before checking for a false data sharing load location.

19. The apparatus of claim 18 , wherein said processing means further comprises a cache memory.

20. The apparatus of claim 19 , wherein said memory means further comprises instructions for causing said computer processing means to function as a testcase generator.

21. The apparatus of claim 20 , wherein said computer processing means, when functioning as a testcase generator, generates testcases that test the data sharing functionality of said integrated circuit using said predictable false data sharing locations.

22. A computer readable program product comprising: a data sharing processor evaluation mechanism that when executed by a processor generates a testcase thread of code, creates a list of data lines used by said generated testcase thread of code, and generates a list of predictable data sharing locations based on said data line list and a bias hierarchy including checking for false data sharing store locations prior to checking for false data sharing load locations, wherein said list of predictable data sharing locations are available for use by a testcase generator to produce predictable data sharing testcases; and computer readable signal bearing media bearing said test coverage evaluation and adjustment mechanism.

23. The computer readable program product of claim 22 , wherein said signal bearing media comprises recordable media.

24. The computer readable program product of claim 22 , wherein the signal bearing media comprises transmission media.

25. The method for identifying predictable data sharing locations of claim 1 , wherein said list of predictable data sharing locations includes data representative of bytes within said data lines that are not used by said generated testcase thread of code.